Process and apparatus for coding binary signals for numbering images or pictures stored on a recording medium for stop mode reproduction

Claim 2

A process for coding binary image numbering signals to be stored on a recording medium, said binary signals being in the form of a serial bit train, wherein the binary signals are protected against variations encountered during the transcription process by repeating a number of times the lowest weight bit of said serial bit train and retransmitting the redundant serial bit train obtained in this way on a number of occasions, the bits of one part of said redundant trains also being inverted.

Claim 3

A process according to claim 1, wherein the redundant serial bit trains are transmitted three times, the bits of the first and third trains remaining unchanged and the bits of the second train being inverted.

Claim 4

A process according to claim 1, wherein the lowest weight bit of each of the said serial bit trains is repeated five times.

Claim 5

A decoding device for decoding binary image numbering signals stored on a recording medium in the form of a serial bit train, wherein the binary signals are protected against variations encountered during a transcription process by repeating a number of times the lowest weight bit of said serial bit train and retransmitting the redundant serial bit train obtained in this way on a number of occasions, the bits of one part of said redundant trains also being inverted, comprising, members for reading the signals stored on the recording medium and clock and synchronizing signals generating means; first memory store means for recording the successively read redundant serial bit trains, means for inverting a predetermined part of the signals recorded in said first memory store means, first comparison means effecting a first majority vote between the signals present at the output of said memory store means, at the output of said inverting means and at the output of said reading members, combined memory store and serial-parallel conversion means for the complete recording of one of said redundant bit trains resulting from the majority vote, and means for evaluating the repeated value of the lowest weight bit stored in said combined memory store and serial-parallel conversion means to determine if successive redundant bit trains belong to the same image or picture.

Claim 6

A decoding device for decoding binary image numbering signals stored on a recording medium in the form of a serial bit train, wherein the binary signals are protected against variations encountered during a transcription process by repeating a number of times the lowest weight bit of said serial bit train and retransmitting the redundant serial bit train obtained in this way on a number of occasions, the bits of one part of said redundant trains also being inverted, comprising, members for reading the signals stored on the recording medium and clock and synchronizing signals generating means; first memory store means for recording the successively read redundant serial bit trains, means for inverting a predetermined part of the signals recorded in said first memory store means, first comparison means effecting a first majority vote between the signals present at the output of said memory store means, at the output of said inverting means and at the output of said reading members, combined memory store and serial-parallel conversion means for the complete recording of one of said redundant bit trains resulting from the majority vote, and means for evaluating the repeated value of the lowest weight bit stored in said combined memory store and serial-parallel conversion means to determine if successive redundant bit trains belong to the same image or picture.

Claim 7

A device according to claim 4, wherein said evaluating means comprises second memory store means for the temporary recording of the repeated value of the lowest weight bit of the bit train recorded in said combined memory store and serial-parallel conversion means, second comparison means comprising two series of inputs, the first of said input series being connected to the outputs of the second memory store means and the second of said input series is connected to the outputs of said combined memory store and serial-parallel conversion means repeating the lowest weight bit and third comparison means receiving the signals present at the outputs of the second comparison means for effecting a second majority vote.

Claim 8

A device according to claim 5, wherein the second memory store means are constituted by a static memory with parallel outputs and inputs of capacity 5 bits, said second comparison means being constituted by logic exclusive OR gates with two inputs and said third comparison means are constituted by a 3/5 majority vote circuit with 5 inputs.

Claim 9

An apparatus for transmitting audio visual signals written on a recording support in accordance with a track forming a spiral whose turn incorporate in each case two fields belonging to the same picture or to contiguous pictures having a binary image numbering signal reading device according to claim 5, as well as a track jump control pulse generating system, wherein the signal present at the output of the third comparison means of the device is transmitted to the track jump control pulse generating system, authorizing the supply of a track jump control pulse transmitted to the reading members when two contiguous fields belong to the same image or picture.

Claim 10

An apparatus according to claim 7, wherein the second memory store means of the binary image numbering signal reading device store the data for the duration of a field.

Claim 11

A device according to claim 4, wherein the first memory store means comprise a first shift register of capacity 24 bits which receives at its input the signals read by the reading members and a second shift register connected in cascade of the same capacity and in which the first comparison means are constituted by a logic 2/3 majority vote circuit with the inputs, the third input being connected to the output of second shift register, the second input, via an inverter to the output of the first shift register and the first input to the input of said register.

Claim 12

A device according to claim 4, wherein the combined memory store and serial-parallel conversion means are constituted by a shift register with a serial input and parallel outputs of capacity 24 bits.