Hybrid redundancy interface

Abstract

Abstract The interface disclosed herein is capable of operating in the TMR/S (triple modular redundancy with sparing), the comparison, and the simplex modes. The interface controls the interconnection between m1 , . . . , mn identical sending modules and M1 , . . . , Mn identical receiving modules. To this end, there are provided 1, . . . , n control registers which comprise 1, . . . , n bits and an (n+1)th control register which comprises a single bit RS. The register bits are employed to provide n2 forcing functions for the outputs d1, . . . , dn of the sending modules which are represented by the following logical equation: WHEREIN J IS THE BIT NUMBER, 1, . . . , N, I IS THE REGISTER NUMBER 1,..., N, THE SYMBOL N SIGNIFIES MODULO N AND V represents the OR function. The n2 forcing functions are respectively applied in sets of n viz., f1i, f2i, . . . , fni i 1,2, . . . , n to (1, . . . , n)th threshold function circuits, each of the latter circuits producing a ''''1'''' output when > OR = 2 of the inputs thereto are ''''1'''', the outputs of the (1, . . . , n)th threshold function circuits being applied to the M1, . . . , Mn)th receiving modules, respectively. From the register settings and the sending module outputs, there are generated pairs represented by the logical equation Cij (di V Rij V Rji V RS, djRijRji V Rs) for j i+1 (i 1, 3, 5, . . . , n-1) Cij (di V Rij V Rji, djRijRji) for j NOT = i+i WHEREIN THE IJ PAIR IN THE FIRST EQUATION CAN TAKE THE VALUES OF 13, 14, . . . , 1N, 24N, . . . , (N-2)N. From the pairs, (ij), there are generated register triggers having the following equations: A1 +/C12 Lambda M C13 M C14 Lambda M . . . Lambda M C1n A2 +/C21 Lambda M C23 Lambda M C24 Lambda M . . . Lambda M C2n An +/C1n Lambda M C2n Lambda M C3n Lambda M . . . Lambda M C(n 1)n WHEREIN THE SYMBOL Lambda M represents the morphic AND function called the RCCO in U.S. Pat. No. 3,559,167, the symbol + signifies the exclusive OR function on the pair of lines that are outputs of the morphic AND. The (A1, . . . ,An)th triggers are applied to the (1, . . . , n)th bits of the registers respectively, to switch the bits to the opposites of their initial binary states whereby, upon the generation of a register trigger Aj and the consequent switching of register bits R1j, . . . , Rnj to their opposite binary states, sending module mj is disconnected from operation. To operate the interface in the TMR/S mode, initially all of the bits of the (1, . . . , n)th registers are initially set to the 1 state and the bit of the (n+ 1)th register is set to the 0 state. To operate the interface in thE comparison mode, all the bits bearing the same numerical designation as the sending module which are to be compared in the registers bearing the same numerical designations as the sending modules which are to be compared are initially set to the 1 state with all of the other bits set to the 0 state. To operate in the simplex mode, all of the bits in the (1, . . . ,n)th registers except those bearing the same numerical designation as that borne by the register in which they are contained are set to the 0 state, the excepted bits being set to the 1 state. Also, in the simplex mode of operation, the bit of the n+1th register is set to the 1 state.

Inventors

• 👤 W Carter
• 👤 A Wadia

Bibliographic Details