Patent US4337525A successfully refreshed from Google Patents.
US4337525A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Asynchronous circuit responsive to changes in logic level
Assignee: NEC Corp
•
Filing: 1980-04-11
•
Granted: 1982-06-29
•
Expires: 2000-04-11
Abstract
Abstract An integrated circuit operable with low power consumption and high reliability is disclosed. The circuit comprises a logic circuit receiving an input logic signal at its input, detection means for detecting a change in the logic input signal, means responsive to an output of detection means for producing a control signal, and control means responsive to the control signal for setting the logic circuit at a predetermined condition irrespective of the input logic signal.
Inventors
- 👤 Yasuo Akatsuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:08
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/41; G11C11/413; G11C11/417; G11C11/418; G11C8/00; G11C8/06; G11C8/18
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
194 words
A memory device comprising input means for receiving a plurality of input address signals having first and second logic levels, a plurality of memory cell means, access means responsive to said input address signals for selectively accessing said memory cell means, a plurality of detection circuit means, each of said detection circuit means detecting when the associated address signal takes an insensitive level between said first and second logic levels, each of said detection circuit means including a first inverter circuit means having a first threshold voltage corresponding to an upper value of said insensitive level, said first inverter circuit means receiving the associated input address signal, second inverter circuit means having a second threshold voltage corresponding to the lower value of said insensitive level, said second inverter circuit means receiving said associated input address signal, Exclusive OR circuit means receiving output signals of said first and second inverter circuit, and means responsive to an output signal of at least one of said Exclusive OR circuit means for operatively resetting said access means, whereby the operation of said access means is inhibited when at least one of said address signals takes said insensitive level.
Claim 2
Dependent Claim
194 words
A memory device comprising input means for receiving a plurality of input address signals having first and second logic levels, a plurality of memory cell means, access means responsive to said input address signals for selectively accessing said memory cell means, a plurality of detection circuit means, each of said detection circuit means detecting when the associated address signal takes an insensitive level between said first and second logic levels, each of said detection circuit means including a first inverter circuit means having a first threshold voltage corresponding to an upper value of said insensitive level, said first inverter circuit means receiving the associated input address signal, second inverter circuit means having a second threshold voltage corresponding to the lower value of said insensitive level, said second inverter circuit means receiving said associated input address signal, Exclusive OR circuit means receiving output signals of said first and second inverter circuit, and means responsive to an output signal of at least one of said Exclusive OR circuit means for operatively resetting said access means, whereby the operation of said access means is inhibited when at least one of said address signals takes said insensitive level.
Claim 3
Dependent Claim
146 words
A semiconductor memory device comprising means for receiving a plurality input address signals having first and second logic levels, a plurality of memory cell means arrayed in a matrix form of rows and columns, decoder means responsive to a first portion of said input address signals for operatively selecting one of said rows, selection means responsive to a second portion of said address signal for operatively selecting one of said columns, detection means for detecting when at least one of said input address signals takes an intermediate level which is higher than said first logic level and lower than said second logic level, said detection means generating a detection signal only when at least one of said input address signals takes said intermediate level, and means responsive to said detection signal for generating a first control signal for controlling the operation state of said decoder means.
Claim 4
Dependent Claim
146 words
A semiconductor memory device comprising means for receiving a plurality input address signals having first and second logic levels, a plurality of memory cell means arrayed in a matrix form of rows and columns, decoder means responsive to a first portion of said input address signals for operatively selecting one of said rows, selection means responsive to a second portion of said address signal for operatively selecting one of said columns, detection means for detecting when at least one of said input address signals takes an intermediate level which is higher than said first logic level and lower than said second logic level, said detection means generating a detection signal only when at least one of said input address signals takes said intermediate level, and means responsive to said detection signal for generating a first control signal for controlling the operation state of said decoder means.
Claim 5
Dependent Claim
87 words
The memory according to claim 2, in which said detection means includes first means having a first threshold voltage, second means having a second threshold voltage which is higher than said first threshold voltage, both said first and second means receiving the same input address signal, and third means for detecting when said address signal has a voltage which is higher than said first threshold voltage and lower than said second threshold voltage, whereby said intermediate level of the address signal is detected by said third means.
Claim 6
Dependent Claim
75 words
The memory device according to claim 2, further comprising means responsive to said detection signal for generating a second control signal, means for receiving a write control signal, means for receiving a write data signal, means for substantially synchronizing said write control signal with said second control signal to produce an inner write signal, and means responsive to said inner write signal for writing said write data signal into one of said memory cell means.
Claim 7
Dependent Claim
24 words
The memory according to claim 2, in which each of said memory cell means includes both N-channel insulated-gate field-effect transistors and P-channel insulated-gate-field-effect transistors.
Claim 8
Dependent Claim
25 words
The memory device according to claim 2, in which said access means is enabled through its reset state in response to said first control signal.
Claim 9
Dependent Claim
113 words
The memory device according to claim 2, in which said detection means includes a plurality pairs of inverter circuit members, each pair of said pairs of inverter circuit means including a first inverter circuit means having a first value of threshold voltage and a second inverter circuit means having a second value of threshold voltage, said first value being different from said second value, said first and second inverter circuit means having a common input for receiving one of said input address signals, and a plurality of Exclusive OR gate means, each of said Exclusive-OR gate means receiving a pair of outputs of an associated one pair of said pairs of inverter circuits.
Claim 10
Dependent Claim
92 words
An integrated circuit comprising logic circuit means having an input terminal, means for supplying said input terminal with a logic signal having first and second binary logic levels, detection means for detecting when said logic signal takes an insensitive level between said first and second logic levels, said insensitive level being unclassifiable into binary logic levels for said logic circuit, signal means responsive to said detection means for producing a control signal, and means responsive to said control signal for forcibly setting an output of said logic circuit at a predetermined state.
Claim 11
Dependent Claim
92 words
An integrated circuit comprising logic circuit means having an input terminal, means for supplying said input terminal with a logic signal having first and second binary logic levels, detection means for detecting when said logic signal takes an insensitive level between said first and second logic levels, said insensitive level being unclassifiable into binary logic levels for said logic circuit, signal means responsive to said detection means for producing a control signal, and means responsive to said control signal for forcibly setting an output of said logic circuit at a predetermined state.
Claim 12
Dependent Claim
93 words
The integrated circuit according to claim 8, in which said detection means includes first means having a first threshold voltage, second means having a second threshold voltage which is different from said first threshold voltage, both of said first and said second means receiving said binary logic signal at their inputs, and means for comparing the output of said first means with the output of said second means, said comparing means generating an output signal when the output of said first means does not substantially coincide with the output of said second means.
Claim 13
Dependent Claim
139 words
A memory integrated circuit comprising input means for receiving a plurality of input address signals, a plurality of memory cell means, access means for selectively accessing said memory cell means, means for receiving a write command signal, means for receiving a write data signal which is not classified into binary logic levels, detection means for detecting non-logic level in said input address signals, said non-logic levels being non-classifiable into said binary logic levels, signal means responsive to an output of said detection means for producing a control signal, means for substantially synchronizing said write command signal with said control signal to produce an inner command signal, means for resetting said access means substantially in response to said control signal, and means responsive to said inner command signal for writing said write data signal into one of said memory cells.
Claim 14
Dependent Claim
139 words
A memory integrated circuit comprising input means for receiving a plurality of input address signals, a plurality of memory cell means, access means for selectively accessing said memory cell means, means for receiving a write command signal, means for receiving a write data signal which is not classified into binary logic levels, detection means for detecting non-logic level in said input address signals, said non-logic levels being non-classifiable into said binary logic levels, signal means responsive to an output of said detection means for producing a control signal, means for substantially synchronizing said write command signal with said control signal to produce an inner command signal, means for resetting said access means substantially in response to said control signal, and means responsive to said inner command signal for writing said write data signal into one of said memory cells.
References Cited (Backward Citations)
JPS554735A
Cited
JPS5528542A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-06-28 | 1985-12-28 | 1986-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-06-28 | 1989-12-28 | 1990-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-06-28 | 1993-12-28 | 1994-06-29 | $7700.00 | Window Closed / Lapsed |