Error correction encoding and decoding system

Claim 2

An encoding and decoding system for digital information having a rectangular array of bits including k 1 bits in a first direction and k 2 bits in a second direction orthogonal to the first direction which system comprises encoding means including an encoding adapting circuit for codes C 2 for dividing the k 1 bits in the first direction into b bits apiece, and forming a plurality of k 2 ×b bit rectangular arrays each including the b bits in the first direction and the k 2 bits in the second direction, a C 2 encoder for encoding the plurality of k 2 ×b bit rectangular arrays into a plurality of n 2 ×b bit rectangular arrays each including the b bits in the first direction and n 2 bits in the second direction, a C 1 encoder for encoding the k 1 bits in the first direction into n 1 bits by adding n 1 -k 1 check bits to the k 1 bits in the first direction, and a timing generator circuit for generating timing signals for controlling the operation of said encoding means to thereby encode the digital information into a codeword of a generalized product code including the n 1 bits in the first direction and the n 2 bits in the second direction; and decoding means operatively connected to said encoding means by a transmission means for decoding the digital information encoded by the encoding means; wherein said C 1 and C 2 encoders are operative to encode in response to said timing signals of said timing generator and wherein either said C 1 encoder or said C 2 encoder provides said generalized product code.

Claim 3

An encoding and decoding system for digital information as claimed in claim 1, wherein the encoding means further includes an information matrix forming circuit for forming digital information not originally arranged in a rectangular array of bits into a rectangular array of bits including k 1 and k 2 bits in the first and second directions respectively; wherein said information matrix forming circuit and said C 1 and C 2 encoders are operatively connected together and wherein said digital information from said information matrix forming circuit is encoded by either said C 1 or C 2 encoders.

Claim 4

An encoding and decoding system for digital information as claimed in claim 2, wherein the information matrix forming circuit includes a pair of RAM devices, selector means connected to the pair of RAM devices to alternately place said RAM devices in their write and read cycles of operation and another selector means connected to the pair of RAM devices to read out data from the RAM device operated in its read cycle.

Claim 5

An encoding and decoding system for digital information as claimed in claim 1, wherein the encoding adapting circuit for the code C 2 comprises delay circuits.

Claim 6

An encoding and decoding system as claimed in claim 4, wherein the encoding adapting circuit for the code C 2 includes a plurality of series combinations of b 1-bit delay circuits one for each row in the first direction, each of the delay circuits delaying an input applied thereto by one bit.

Claim 7

An encoding and decoding system for digital information as claimed in claim 4, wherein the encoding adapting circuit for the code C 2 includes RAM means and control circuit means for controlling addresses in the RAM means.

Claim 8

An encoding and decoding system for digital information as claimed in claim 1, wherein the decoding means is disposed on the receiver side to receive a codeword of a generalized product code in the form of the rectangular array including the n 1 and n 2 bits in the first and second directions respectively through a selected one of a group of channels and a record medium and wherein the decoding means includes a plurality of C 1 decoders one for every k 2 bits in the second direction for decoding the k 1 bits in the first direction from the n 1 bits in the first direction, a received word-of-code C 2 forming circuit for dividing an outputs from the C 1 decoders into b bits apiece and forming a plurality of rectangular arrays including b bits in the first direction and n 2 bits in the second direction, and a C 2 decoder for decoding the rectangular arrays of k 2 ×b bits from the rectangular arrays of n 2 ×b bits.

Claim 9

An encoding and decoding system for digital information as claimed in claim 7, wherein the received work-of-code C 2 forming circuit includes a plurality of series combinations of b 1-bit delay circuits one for each row in the second direction, each of the delay circuits delaying an input applied thereto by one bit.

Claim 10

An encoding and decoding system for digital information as claimed in claim 7, wherein the received word-of-code C 2 forming circuit includes RAM means and control circuit means for controlling addresses in the RAM means.

Claim 11

An encoding and decoding system for digital information having a rectangular array of bits including k 1 bits in a first direction and k 2 bits in a second direction orthogonal to the first direction which system comprises encoding means including an encoding adapting circuit for codes C 2 for dividing the k 1 bits in the first direction into b bits apiece, and for forming a plurality of k 2 ×b bit rectangular arrays each including the b bits in the first direction and the k 2 bits in the second direction, a C 2 encoder for encoding the plurality of k 2 ×b bit rectangular arrays into a plurality n 2 ×b bit rectangular arrays each including the b bits in the first direction and n 2 bits in the second direction, a C 1 encoder for encoding the k 1 bits in the first direction into n 1 bits by adding n 1 -k 1 check bits to the k 1 bits in the first direction, and a timing generator circuit for generating timing signals for controlling the operation of said encoding means to thereby encode the digital information into a codeword of a generalized product code including the n 1 bits in the first direction and the n 2 bits in the second direction; and decoding means operatively connected to said encoding means by a transmission means for decoding the digital information encoded by the encoding means; wherein said C 1 and C 2 encoders are operative to encode in response to said timing signals of said timing generator and wherein either said C 1 encoder or C 2 encoder provides said generalized product code of said encoding means; wherein the encoding means further includes an information matrix forming circuit for forming digital information not originally arranged in a rectangular array of bits into a rectangular array of bits including the k 1 and k 2 bits in the first and second directions respectively; wherein the decoding means is disposed on the receiver side to receive a codeword of a generalized product code in the form of the rectangular array including the n 1 and n 2 bits in the first and second directions respectively through a selected one of a group of channels and a record medium and wherein the decoding means includes a plurality of C 1 decoders one for every k 2 bits in the first direction for decoding the k 1 bits in the first direction from the n 1 in the first direction, a received word-of-code C 2 forming circuit for dividing an outputs from the C 1 decoders into b bits apeice and forming a plurality of rectangular arrays including b bits in the first direction and n 2 bits in the second direction, and a C 2 decoder for decoding the rectangular arrays of k 2 ×b bits from the rectangular arrays of n 2 ×b bits; wherein the decoding means further includes an information matrix reproducing circuit for reproducing the rectangular array including the k 1 and k 2 bits in the first and second directions respectively from an output from the C 2 decoder.

Claim 12

An encoding and decoding system for digital information having a rectangular array of bits including k 1 bits in a first direction and k 2 bits in a second direction orthogonal to the first direction which system comprises encoding means including an encoding adapting circuit for codes C 2 for dividing the k 1 bits in the first direction into b bits apiece, and for forming a plurality of k 2 ×b bit rectangular arrays each including the b bits in the first direction and the k 2 bits in the second direction, a C 2 encoder for encoding the plurality of k 2 ×b bit rectangular arrays into a plurality n 2 ×b bit rectangular arrays each including the b bits in the first direction and n 2 bits in the second direction, a C 1 encoder for encoding the k 1 bits in the first direction into n 1 bits by adding n 1 -k 1 check bits to the k 1 bits in the first direction, and a timing generator circuit for generating timing signals for controlling the operation of said encoding means to thereby encode the digital information into a codeword of a generalized product code including the n 1 bits in the first direction and the n 2 bits in the second direction; and decoding means operatively connected to said encoding means by a transmission means for decoding the digital information encoded by the encoding means; wherein said C 1 and C 2 encoders are operative to encode in response to said timing signals of said timing generator and wherein either said C 1 encoder or C 2 encoder provides said generalized product code of said encoding means; wherein the encoding means further includes an information matrix forming circuit for forming digital information not originally arranged in a rectangular array of bits into a rectangular array of bits including the k 1 and k 2 bits in the first and second directions respectively; wherein the decoding means is disposed on the receiver side to receive a codeword of a generalized product code in the form of the rectangular array including the n 1 and n 2 bits in the first and second directions respectively through a selected one of a group of channels and a record medium and wherein the decoding means includes a plurality of C 1 decoders one for every k 2 bits in the first direction for decoding the k 1 bits in the first direction from the n 1 in the first direction, a received word-of-code C 2 forming circuit for dividing an outputs from the C 1 decoders into b bits apeice and forming a plurality of rectangular arrays including b bits in the first direction and n 2 bits in the second direction, and a C 2 decoder for decoding the rectangular arrays of k 2 ×b bits from the rectangular arrays of n 2 ×b bits; wherein the decoding means further includes an information matrix reproducing circuit for reproducing the rectangular array including the k 1 and k 2 bits in the first and second directions respectively from an output from the C 2 decoder.

Claim 13

An encoding and decoding system for digital information as claimed in claim 1 wherein the decoding means further includes an erasure weight calculation circuit and an erasure location calculation circuit for producing respectively erasure weight information and erasure location information indicating errors detected in codes C 1 and means for correcting codes C 2 by utilizing the erasure weight information and erasure location information obtained from decoding code C 1 .

Claim 14

An encoding and decoding system for digital information having a rectangular array of bits including k 1 bits in a first direction and k 2 bits in a second direction orthogonal to the first direction which system comprises encoding means including an encoding adapting circuit for codes C 2 for dividing the k 1 bits in the first direction into b bits apiece, and forming a plurality of k 2 ×b bit rectangular arrays each including the b bits in the first direction and the k 2 bits in the second direction, a C 2 encoder for encoding the k 1 bits in the first direction into n 1 bits by adding n 1 -k 1 check bits to the k 1 bits in the first direction, and a timing generator circuit for generating timing signals for controlling the operation of said encoding means to thereby encode the digital information into a codeword of a generalized product code including the n 1 bits in the first direction and the n 2 bits in the second direction; and decoding means operatively connected to said encoding means by a transmission means for decoding the digital information encoded by the encoding means; wherein said C 1 and C 2 encoders are operative to encode in response to said timing signals of said timing generator and wherein either said C 1 encoder or C 2 encoder provides said generalized product code of said encoding means; wherein the encoding means further includes an information matrix forming circuit for forming digital information not originally arranged in a rectangular array of bits into a rectangular array of bits including the k 1 and k 2 bits in the first and second directions respectively; wherein the decoding means is disposed on the receiver side to receive a codeword of a generalized product code in the form of the rectangular array including the n 1 and n 2 bits in the first and second directions respectively through a selected one of a group of channels and a record medium and wherein the decoding means includes a plurality of C 1 decoders one for every k 2 bits in the first direction for decoding the k 1 bits in the first direction from the n 1 bits in the first direction, a received word-of-code C 2 forming circuit for dividing an outputs from the C 1 decoders into b bits apiece and forming a plurality of rectangular arrays including b bits in the first direction and n 2 bits in the second direction, and a C 2 decoder for decoding the rectangular arrays of k 2 ×b bits from the rectangular arrays of n 2 ×b bits; wherein the decoding means further includes an erasure weight calculation circuit and an erasure location calculation circuit for producing respectively erasure weight information and erasure location information indicating errors detected in codes C 1 and means for correcting codes C 2 by utilizing the erasure weight information and erasure location information obtained from decoding the code of C 1 .

Claim 15

An encoding and decoding system for digital information having a rectangular array of bits including k 1 bits in a first direction and k 2 bits in a second direction orthogonal to the first direction which system comprises encoding means including an encoding adapting circuit for codes C 2 for dividing the k 1 bits in the first direction into b bits apiece, and forming a plurality of k 2 ×b bit rectangular arrays each including the b bits in the first direction and the k 2 bits in the second direction, a C 2 encoder for encoding the k 1 bits in the first direction into n 1 bits by adding n 1 -k 1 check bits to the k 1 bits in the first direction, and a timing generator circuit for generating timing signals for controlling the operation of said encoding means to thereby encode the digital information into a codeword of a generalized product code including the n 1 bits in the first direction and the n 2 bits in the second direction; and decoding means operatively connected to said encoding means by a transmission means for decoding the digital information encoded by the encoding means; wherein said C 1 and C 2 encoders are operative to encode in response to said timing signals of said timing generator and wherein either said C 1 encoder or C 2 encoder provides said generalized product code of said encoding means; wherein the encoding means further includes an information matrix forming circuit for forming digital information not originally arranged in a rectangular array of bits into a rectangular array of bits including the k 1 and k 2 bits in the first and second directions respectively; wherein the decoding means is disposed on the receiver side to receive a codeword of a generalized product code in the form of the rectangular array including the n 1 and n 2 bits in the first and second directions respectively through a selected one of a group of channels and a record medium and wherein the decoding means includes a plurality of C 1 decoders one for every k 2 bits in the first direction for decoding the k 1 bits in the first direction from the n 1 bits in the first direction, a received word-of-code C 2 forming circuit for dividing an outputs from the C 1 decoders into b bits apiece and forming a plurality of rectangular arrays including b bits in the first direction and n 2 bits in the second direction, and a C 2 decoder for decoding the rectangular arrays of k 2 ×b bits from the rectangular arrays of n 2 ×b bits; wherein the decoding means further includes an erasure weight calculation circuit and an erasure location calculation circuit for producing respectively erasure weight information and erasure location information indicating errors detected in codes C 1 and means for correcting codes C 2 by utilizing the erasure weight information and erasure location information obtained from decoding the code of C 1 .

Claim 16

An encoding and decoding system for digital information as claimed in claims 11 or 12, wherein the erasure weight calculation circuit includes an n 2 bit parallel in-serial out shift register, a b bit binary counter and a counter decoder circuit and the erasure location calculation circuit comprises an ROM device including addresses determining input patterns applied thereto and output patterns preliminarily stored at the addresses.

Claim 17

An encoding and decoding system for digital information as claimed in claims 11 or 12 wherein the erasure weight calculation circuit comprises an ROM device including addresses determining input patterns applied thereto and output patterns preliminarily stored at the addresses and the erasure location calculation circuit comprises an ROM device including addresses determining input patterns applied thereto and output patterns preliminarily stored at the addresses.