Error correction apparatus and method

Claim 2

Apparatus for providing data groups from a memory to a destination circuitry comprising: a. a first path from said memory to said destination circuitry; and b. a second path from said memory to said destination circuitry, said second path including error detection and correction circuitry for detecting at least one data group from said memory having an error therein and substituting a corrected data group therefor; and c. a control unit operatively connected to said error detection and correction circuitry and to said destination circuitry for indicating said error, said destination circuitry responding to said control unit to replace said one data group with said corrected data group and to receive subsequent data groups from said error detection and correction circuitry.

Claim 3

Apparatus for providing at least one corrected data group, each data group being transferred from a memory comprising: a. data switch connected to receive and transfer as an output thereof data groups from said memory; b. error detection and correction circuitry operatively connected to said memory and to said data switch for providing each corrected data group to said data switch if one of said data groups contains a correctable error, said data switch responding to said error detection and correction circuitry having corrected said error for receiving and transferring said corrected data group and subsequent data groups in sequence from said error detection and correction circuitry.

Claim 4

Apparatus for providing at least one corrected data group, each data group being transferred from a memory comprising: a. data switch connected to receive and transfer as an output thereof data groups from said memory; b. error detection and correction circuitry operatively connected to said memory and to said data switch for providing each corrected data group to said data switch if one of said data groups contains a correctable error, said data switch responding to said error detection and correction circuitry having corrected said error for receiving and transferring said corrected data group and subsequent data groups in sequence from said error detection and correction circuitry.

Claim 5

Apparatus receiving a data stream divided into data groups from a memory in a predetermined sequence, comprising: a. error detection and correction circuitry connected to receive said data groups in said predetermined sequence for substituting a corrected data group within said predetermined sequence for each of said data groups having an error therein; and b. a data switch operatively connected to selectively transfer said data groups from said memory in said predetermined sequence and c. from said error detection and correction circuitry in said predetermined sequence including said corrected data group after a correctable error is detected.

Claim 6

Apparatus receiving a data stream divided into data groups from a memory in a predetermined sequence, comprising: a. error detection and correction circuitry connected to receive said data groups in said predetermined sequence for substituting a corrected data group within said predetermined sequence for each of said data groups having an error therein; and b. a data switch operatively connected to selectively transfer said data groups from said memory in said predetermined sequence and c. from said error detection and correction circuitry in said predetermined sequence including said corrected data group after a correctable error is detected.

Claim 7

Apparatus receiving a data stream divided into data groups in a predetermined sequence from a memory for providing a corrected data group for each data group having an error therein to a destination circuitry, comprising: a. an error detection and correction circuitry operatably connected to receive said data stream for substituting within said predetermined sequence corrected data groups corresponding to data groups having errors therein to form a corrected data stream, said error detection and correction circuitry generating signals when a corrected data group is substituted; b. a data switch operatively connected to receive said data stream from said memory and to receive said corrected data stream from said error detection and correction circuitry, said data switch connected to said destination circuitry for selectively providing said data stream thereto and in response to said signal for providing said corrected data stream thereto.

Claim 8

Apparatus receiving a data stream divided into data groups in a predetermined sequence from a memory for providing a corrected data group for each data group having an error therein to a destination circuitry, comprising: a. an error detection and correction circuitry operatably connected to receive said data stream for substituting within said predetermined sequence corrected data groups corresponding to data groups having errors therein to form a corrected data stream, said error detection and correction circuitry generating signals when a corrected data group is substituted; b. a data switch operatively connected to receive said data stream from said memory and to receive said corrected data stream from said error detection and correction circuitry, said data switch connected to said destination circuitry for selectively providing said data stream thereto and in response to said signal for providing said corrected data stream thereto.

Claim 9

Apparatus as set forth in claim 4 including a second data switch connected to receive said data stream from said memory in said predetermined sequence and from said error detection and correction circuitry for selectively providing said data stream to a second destination circuitry and in response to said signals said corrected stream thereto.

Claim 10

Apparatus as set forth in claim 4 wherein said error detection and correction circuitry produces a first signal if an uncorrectable error is detected and said destination circuitry aborts in response thereto.

Claim 11

Apparatus as set forth in claim 4 wherein said error detection and correction circuitry produces a second signal when said corrected data group is substituted and said destination circuitry is opertably connected to receive said second signal for ignoring said data group having an error therein and corresponding to said corrected data group.

Claim 12

Apparatus as set forth in claim 4 wherein said error detection and correction circuitry receives an address for each data group within said memory for detecting errors in addressing.