US4336599A
Expired / Lapsed
US
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Circuit for performing a square root calculation
Assignee: Unisys Corp
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Filing: 1980-06-09
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Granted: 1982-06-22
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Expires: 2000-06-09
Abstract
Abstract There is disclosed a circuit which is capable of performing a square root function in a floating point processor in such a manner that the speed of operation is increased by approximately 50%.
Inventors
- 👤 Wilson T. C. Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:37
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/552; G06F7/5525
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
145 words
A circuit for performing the squareroot function on a floating point number comprising, a source for supplying a floating point number, instruction register means connected to receive said floating point number from said source, decoder means connected to receive said floating point number from said instruction register means, field select multiplexer means connected to receive an address signal from said decoder means and a coded signal from said instruction register means, control store address multiplexer means also connected to receive a decode address signal from said decoder means and a field select address from said field select multiplexer means, and control store means for storing microprogram information therein and connected to receive a current address from said control store address multiplexer means such that the next microinstruction is selected to designate constants for linear approximations which depend upon the value of the floating point number.
Claim 2
Dependent Claim
145 words
A circuit for performing the squareroot function on a floating point number comprising, a source for supplying a floating point number, instruction register means connected to receive said floating point number from said source, decoder means connected to receive said floating point number from said instruction register means, field select multiplexer means connected to receive an address signal from said decoder means and a coded signal from said instruction register means, control store address multiplexer means also connected to receive a decode address signal from said decoder means and a field select address from said field select multiplexer means, and control store means for storing microprogram information therein and connected to receive a current address from said control store address multiplexer means such that the next microinstruction is selected to designate constants for linear approximations which depend upon the value of the floating point number.
Claim 3
Dependent Claim
19 words
The circuit recited in claim 2 wherein, said instruction register means includes instruction buffer means connected to said source.
Claim 4
Dependent Claim
30 words
The circuit recited in claim 2 wherein, said instruction buffer means receives signals from said source and supplies complementary output signals to said instruction register means and said decoder means.
Claim 5
Dependent Claim
14 words
The circuit recited in claim 1 wherein, said source includes a floating point processor.
Claim 6
Dependent Claim
24 words
The circuit recited in claim 1 wherein, said control store means comprises buffer means for producing an output signal representative of different input signals.
Claim 7
Dependent Claim
29 words
The circuit recited in claim 5 wherein, said current address is supplied to a Here Plus One register which supplies a sequential address to said control store multiplexer means.
Claim 8
Dependent Claim
24 words
The circuit recited in claim 6 wherein, said Here Plus One register supplies the address of the microinstruction presently under execution incremented by one.
Claim 9
Dependent Claim
21 words
The circuit recited in claim 5 including, subroutine return stack means connected to supply a signal to said control store means.
Claim 10
Dependent Claim
27 words
The circuit recited in claim 8 wherein, said subroutine return stack comprises at least one register which stores microinstruction addresses for use in high speed subroutine returns.
Claim 11
Dependent Claim
20 words
The circuit recited in claim 5 including, control logic means for controlling the operation of each of said multiplexer means.
Claim 12
Dependent Claim
29 words
The circuit recited in claim 5 wherein, said control store buffer means produces an output signal representative of at least portions of the next address for the microinstruction operation.
Claim 13
Dependent Claim
26 words
The circuit recited in claim 1 wherein, said current address includes fields of bits which represent a page address, a column address and a row address.
Claim 14
Dependent Claim
18 words
The circuit recited in claim 1 including, data bus means connecting said source to said instruction register means.
Claim 15
Dependent Claim
19 words
The circuit recited in claim 13 including, storage means connected to said data bus means for supplying instructions thereto.
Claim 16
Dependent Claim
13 words
The circuit recited in claim 14 wherein, said storage means comprises memory means.
Claim 17
Dependent Claim
56 words
The circuit recited in claim 1 wherein, said source provides data to said instruction register means such that said instruction register means can decode said data and provide signals to said field select multiplexer means and said control store address multiplexer means to control the operation of a microprogram as a function of the decoded data.
Claim 18
Dependent Claim
17 words
The circuit recited in claim 1 wherein, said instruction register means stores an instruction currently in execution.
Claim 19
Dependent Claim
24 words
The circuit recited in claim 17 wherein, said instruction can be in the form of a data word representative of data from said source.
Claim 20
Dependent Claim
38 words
The circuit recited in claim 1 wherein, said decoder means includes pre-decoder means which performs a mapping operation on the signal recieved from said instruction register means and supplies a signal to said control store address multiplexer means.
Claim 21
Dependent Claim
34 words
The circuit recited in claim 1 wherein, said field select multiplexer means selects a field from the signals supplied by said instruction register means for specifying the next row address in field select addressing.
Claim 22
Dependent Claim
20 words
The circuit recited in claim 1 wherein, said control store means stores all of the microinstructions used by the circuit.
References Cited (Backward Citations)
US3049296A
Cited
US3280314A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-06-21 | 1985-12-21 | 1986-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-06-21 | 1989-12-21 | 1990-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-06-21 | 1993-12-21 | 1994-06-22 | $7700.00 | Window Closed / Lapsed |