Digital circuitry for determining a binary square root

Claim 1

IN A DIGITAL COMPUTER, MEANS FOR GENERATING THE SQUARE ROOT OF A NUMBER, COMPRISING: (A) A FIRST REGISTER FOR INITIALLY STORING SAID NUMBER AND FOR SUBSEQUENTLY STORING PARTIAL RESULTS DEVELOPED DURING SUCCESSIVE CYCLES; (B) A SECOND REGISTER FOR INITALLY STORING A TRIAL SQUARE ROOT OF SAID NUMBER AND FOR SUBSEQUENTLY STORING THE PARTIALLY DEVELOPED ROOT OF SAID NUMBER; (C) A THIRD REGISTER FOR INITIALLY STORING A PREDETERMINED CONSTANT AND FOR SUBSEQUENTLY STORING A MULTIPLE OF SAID CONSTANT; (D) ARITHMETIC MEANS FOR SUBSTRACTING THE CONTENTS OF SAID SECOND REGISTER FROM THE CONTENTS OF SAID FIRST REGISTER, LEAVING THE DIFFERENCE IN SAID FIRST REGISTER, AND FOR PRODUCING AN OUVERDRAFT SIGNAL IN THE EVENT THAT THE CONTENTS OF SAID SECOND REGISTER EXCEEDS THE CONTENTS OF SAID FIRST REGISTER; (E) MEANS OPERATIVE IN THE ABSENCE OF SAID OVERDRAFT SIGNAL FOR SHIFTING SAID DIFFERENCE ONE PLACE TOWARD THE MOST SIGNIFICANT DIGIT POSITION AND FOR SHIFTING THE CONTENTS OF SAID THIRD REGISTER ONE PLACE TOWARD THE LEAST SIGNIFICANT DIGIT POSITION; (F) MEANS INCLUDING SAID ARITHMETIC MEANS OPERATIVE IN THE ABSENCE OF SAID OVERDRAFT SIGNAL FOR FORMING THE SUM OF THE SHIFTED CONTENTS OF SAID THIRD REGISTER WITH THE THEN CONTENTS OF SAID SECOND REGISTER IN SAID SECOND REGISTER; (G) MEANS RESPONSIVE TO THE PRESENCE OF SAID OVERDRAFT SIGNAL FOR SHIFTING THE CONTENTS PRESENT IN SAID FIRST REGISTER PRIOR TO THE SUBSTRACTION OF THE CONTENTS OF SAID SECOND REGISTER FROM THE CONTENTS OF SAID FIRST REGISTER, ONE PLACE TOWARD THE MOST SIGNIFICANT DIGIT POSITION AND FOR SHIFTING THE CONTENTS OF SAID THIRD REGISTER ONE PLACE TOWARD THE MOST SIGNIFICANT DIGIT POSITION; (H) AND MEANS INCLUDING SAID ARITHMETIC MEANS RESPONSIVE TO THE PRESENCE OF SAID OVERDRAFT SIGNAL FOR FORMING THE SUN MODULA-2 OF THE CONTENTS OF SAID SECONE AND THIRD REGISTERS.