Semiconductor memory cell with clocked voltage supply from data lines

Claim 1

An array of rows and columns of identical static self-refresh memory cells, each cell comprising a pair of cross-coupled driver transistors and first and second pairs of coupling transistors, each of the transistors being an insulated-gate field-effect transistor of the same channel conductivity type having a source-to-drain path and a gate, each cell having a pair of storage nodes with no d.c. path from the storage nodes to a voltage supply, a plurality of pairs of complementary data lines providing the column lines for the array of cells, each of the first pair of coupling transistors having their source-to-drain paths connected between one of the data lines of a pair and one of the storage nodes of a cell, means including the second pair of coupling transistors for refreshing the pair of storage nodes during a first time period, a plurality of first conductive means providing array address lines for applying operating voltage to the gate electrodes of the second pair of transistors in each of the cells during said first time period, and second conductive means providing a row address line for applying operating voltage to the gate electrodes of the first pair of transistors in each of the cells during a second time period for a selected row in each operating cycle, the first conductive means not applying operating voltage to the control electrodes of said first pair of transistors during said second time period during a refresh cycle.