One-transistor dynamic ram with poly bit lines

Claim 1

An MOS integrated semiconductor memory, comprising: a semiconductor substrate; a plurality of memory locations arranged in lines and columns; each memory location having two one-transistor memory cells on the substate; each memory cell comprising an MOS memory capacitor and an MOS transistor; a word line running in the line direction arranged to control gates of the two one-transistor memory cells of a memory location; the two MOS transistors at each memory location each being coupled to a respective bit line which runs at one side of the memory location in the column direction and between two adjacent columns; for each one-transistor memory cell at the memory location an electrode of the MOS memory capacitor being formed by a first polysilicon layer and a gate of the MOS transistor being formed by a second polysilicon layer; the bit line associated with each one-transistor memory cell being formed by a third polysilicon layer as a polysilicon path; each bit line being coupled to the MOS transistor of each one-transistor memory cell by a respective limited doped connection zone in the semiconductor substrate; and at each memory cell one of the polysilicon layer bit lines being positioned in insulated fashion over the first polysilicon layer which forms the electrode of the memory capacitor of the respective one-transistor memory cell, the first polysilicon layer passing completely under the bit line separating the two adjacent columns of memory cells and directly connecting electrodes of the MOS memory capacitors in at least one memory cell in each of the two adjacent columns.