Signal processing circuit for solid-state camera

Claim 2

A signal processing circuit for use in a solid-state camera having a solid-state image sensor for converting picture elements composing an optical image to electrical signals, the circuit comprising: means for sequentially sensing the electrical signals representing the picture elements output of said solid-state image sensor; means for converting the output signal of said sensing means into a first and a second signal which are respectively in phase with and opposite phase to the output signal of said sensing means; first and second integrators for integrating said first and second signals for each picture element respectively; and a differential amplifier for producing an output signal representing a difference between two outputs of said first and second integrators as a video signal.

Claim 3

A signal processing circuit according to claim 1, wherein said sensing means sequentially sensing the electrical signals representing the picture elements in accordance with incontinuous scanning pulses, and said first and second integrators respectively integrate said first and second signals in response to a reset pulse, which has the same frequency as said scanning pulse and a predetermined phase difference therewith, for a predetermined period associated with said reset pulse and then outputting and resetting the integrated values in response to the same reset pulse.

Claim 4

A signal processing circuit according to claim 2, wherein said converting means includes first and second transistors arranged in a differential amplifier configuration for converting the output signal of said sensing means into said first and second signals, said first integrator including a first capacitor one end of which is connected to the collector of said first transistor and a first MOS-type switching element with a controlled electrode applied with said reset pulse one end of which is connected to the collector of said first transistor and the other end thereof is connected to a DC power source through a first load, and said second integrator including a second capacitor one end of which is connected to the collector of said second transistor and a second MOS-type switching element with a controlled electrode applied with said reset pulse one end of which is connected to the collector of said second transistor and the other end thereof is connected to said DC power source through a second load, whereby the terminal voltages across said first and second loads are respectively applied to said differential amplifier as the outputs of said first and second integrators.

Claim 5

A signal processing circuit according to claim 3, wherein each of said first and second switching elements is a MOS FET.

Claim 6

A signal processing circuit according to claim 2, wherein said converting means includes first and second transistors arranged in a differential amplifier configuration for converting the output signal of said sensing means into said first and second signals, said first integrator including a first capacitor one end of which is connected to the collector of said first transistor and the other end thereof is applied with said reset pulse and further including a first bipolar-type rectifying element one end of which is connected to the collector of said first transistor and the other end thereof is connected to a first DC power source through a first load, and said second integrator including a second capacitor one end of which is connected to the collector of said second transistor and the other end thereof is applied with said reset pulse and further including a second bipolar-type rectifying element one end of which is connected to the collector of said second transistor and the other end thereof is connected to said first DC power source through a second load, whereby the terminal voltages across said first and second loads are respectively applied to said differential amplifier as the outputs of said first and second integrators.

Claim 7

A signal processing circuit according to claim 5, wherein each of said first and second rectifying elements is a diode.

Claim 8

A signal processing circuit according to claim 5, wherein each of said first and second rectifying elements is a transistor arranged so as to act as a diode.

Claim 9

A signal processing circuit according to claim 5, wherein said first rectifying element is a third transistor having an emitter connected to the collector of said first transistor, a collector connected to said first load and a base connected to a second DC power source, and said second rectifying element is a fourth transistor having an emitter connected to the collector of said second transistor, a collector connected to said second load and a base connected to said second DC power source.