Patent US4333075A successfully refreshed from Google Patents.
US4333075A
Expired / Lapsed
US
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An analog-to-digital converter accurate relative to the value of the input signal
Assignee: Bendix Corp
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Filing: 1980-03-27
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Granted: 1982-06-01
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Expires: 2000-03-27
Abstract
Abstract A method and apparatus for converting between analog signals and corresponding digital signals that is accurate relative to the actual value of the input signal, and not relative to the upper limit on the analog input signal. The method and apparatus are disclosed in terms of a serial-feed-back A/D converter that performs an A/D conversion through a plurality of cycles equal in number to the number of bits in the digital output word. In each cycle a comparison voltage is tested to determine if the bit output for the cycle is high or low. The comparison voltage is the amplified difference of the comparison voltage for the preceding cycle and another reference signal. The scale factor for the amplification of the difference between the two signals is one value if the bit value for the preceding cycle was high, and another complementary value if the bit value for the preceding cycle is low. The companion method and apparatus for converting a non-binary digital signal into a corresponding analog signal is also disclosed.
Inventors
- 👤 Arliss E. Whiteside
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:33
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/40; H03M1/66; H03M1/72
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
369 words
A non-binary analog to digital converter comprising: means receiving clock signals from an external source for repetitively generating a predetermined set of sequential timing signals including a first timing signal coincident with the first of said predetermined set of sequential timing signals; first switch means having a first input receiving an input analog signal, a second input receiving a feedback signal V C , a third input receiving said first timing signal, and an output, said first switch means having a first state transmitting said analog signal to said output in response to said first timing signal and a second state transmitting said feedback signal V C to said output in response to the absence of said first timing signal; analog signal storage means for storing an analog signal; second switch means for transmitting the signal from the output of said first switch means to said analog storage means in response to a clock signal and transmitting the signal stored in said analog storage means having a value V P to an output in response to the absence of a clock signal; comparator means having a negative input receiving a reference signal kV R , a positive input receiving the signal at the output of the first switch means, and an output, said comparator means generating a digital output bit having a first value when the signal from the output of the first switch means is greater than the reference signal kV R and a second value when the signal from the output of the first switch means is less than the reference signal kV R ; and feedback signal generator means receiving said reference signal V R , said stored signal V P , and said digital output bit for generating a first feedback signal V C having a value: V.sub.C =(1/(1-k)) (V.sub.P -kV.sub.R) when said digital bit has said first value and generating a second feedback signal having value V.sub.C =(1/k)V.sub.P when said digital bit has said second value, wherein k has a predetermined value in the range from o<k<1/2; wherein the output is a non-binary digital word comprising the sequentially generated digital bits generated at the output of said comparator means between sequential first timing signals.
Claim 2
Dependent Claim
369 words
A non-binary analog to digital converter comprising: means receiving clock signals from an external source for repetitively generating a predetermined set of sequential timing signals including a first timing signal coincident with the first of said predetermined set of sequential timing signals; first switch means having a first input receiving an input analog signal, a second input receiving a feedback signal V C , a third input receiving said first timing signal, and an output, said first switch means having a first state transmitting said analog signal to said output in response to said first timing signal and a second state transmitting said feedback signal V C to said output in response to the absence of said first timing signal; analog signal storage means for storing an analog signal; second switch means for transmitting the signal from the output of said first switch means to said analog storage means in response to a clock signal and transmitting the signal stored in said analog storage means having a value V P to an output in response to the absence of a clock signal; comparator means having a negative input receiving a reference signal kV R , a positive input receiving the signal at the output of the first switch means, and an output, said comparator means generating a digital output bit having a first value when the signal from the output of the first switch means is greater than the reference signal kV R and a second value when the signal from the output of the first switch means is less than the reference signal kV R ; and feedback signal generator means receiving said reference signal V R , said stored signal V P , and said digital output bit for generating a first feedback signal V C having a value: V.sub.C =(1/(1-k)) (V.sub.P -kV.sub.R) when said digital bit has said first value and generating a second feedback signal having value V.sub.C =(1/k)V.sub.P when said digital bit has said second value, wherein k has a predetermined value in the range from o<k<1/2; wherein the output is a non-binary digital word comprising the sequentially generated digital bits generated at the output of said comparator means between sequential first timing signals.
Claim 3
Dependent Claim
233 words
The analog to digital converter of claim 1 wherein said feedback signal generator means comprises: amplifier means having a positive input receiving said stored signal V P , a negative input, and an output connected to said comparator means and said second switch means; a first resistance R 1 connecting the output of said amplifier means to its negative input; third switch means receiving said reference signal V R at a first input, a common ground signal at a second input, and said digital output bit at a third input, said third switch means transmitting said reference signal V R to a first output in response to said digital output bit signal having said first value and transmitting said ground signal to a second output in response to said digital output bit having said second value; a second resistance R 2 connecting said first output of said third switch means with the negative input to said amplifier means, said second resistance R 2 having an ohmic value related to the ohmic value of said first resistance R 1 according to the equation R.sub.2 =(1-k)/k) R.sub.1 a third resistance R 3 connecting said second output of said third switch means with the negative input to said amplifier means, said third resistance R 3 having an ohmic value related to the ohmic value of said first resistance R 1 according to the equation: R.sub.3 =(k/(1-k))R.sub.1
Claim 4
Dependent Claim
23 words
The analog to digital converter of claim 1 further including means for converting said non-binary digital word to a corresponding binary digital word.
Claim 5
Dependent Claim
58 words
The analog to digital converter of claim 3 wherein said means for converting said non-binary digital word is an addressable storage array storing a set of binary digital words in predetermined storage locations, the address of each binary digital word being defined in terms of it's corresponding non-binary digital word generated by said non-binary analog to digital converter.
Claim 6
Dependent Claim
99 words
The analog to digital converter of claim 4 wherein said feedback signal generator includes elements which must have a precise relationship to each other in order to generate the desired non-binary word and where any errors in the precise relationship between said elements will cause the generated non-binary word to differ from said desired non-binary word, said addressable storage array stores binary words corresponding to the desired non-binary words in the address locations defined by the generated non-binary words thereby correcting for the errors in the generated non-binary word due to errors in the precise relationship between said elements.
Claim 7
Dependent Claim
51 words
The analog to digital converter of claim 2 wherein said means for converting said non-binary word is an addressable storage array containing a corresponding set of binary words the address of each binary word being defined in terms of it's corresponding non-binary word generated by said non-binary analog to digital converter.
Claim 8
Dependent Claim
18 words
The analog to digital converter of claim 6 wherein said addressable storage array is a read only memory.
Claim 9
Dependent Claim
80 words
The analog to digital converter of claim 6 wherein the ohmic values of resistances R 2 and R 3 differ from the desired relationship with respect to resistance R 1 causing the generated non-binary word to differ from the desired non-binary word, said addressable storage array storing said binary words corresponding to the desired non-binary words in the address locations defined by the generated non-binary word; thereby correcting the output binary word for errors in the values of said resistances.
Claim 10
Independent Claim
356 words
A method for converting an analog signal to a corresponding non-binary digital word comprising the steps of: processing clock signals, received from an external clock, to repetitively generate a predetermined set of sequential timing signals including a first timing signal coincident with the first timing signal in each of said predetermined set of sequential timing signals; transmitting said analog signal to the output of a first switch means in response to said first timing signal and transmitting a feedback signal V c to the output of said first switch means in response to the absence of said first timing signal; transmitting by means of a second switch means the signal from the output of said first switch means to an analog storage means in response to each clock signal, to generate a stored signal V P and transmitting the stored signal V P to an output of said second switch means in the absence of said clock signal; comparing the signal at the output of said first switch means to a reference signal kV R to generate during each clock signal a digital output bit having a first value when the value of the signal at the output of said first switch means is greater than the value of said reference signal kV R and a digital output bit having a second value when the value of the signal at the output of said first switch means is less than the value of said reference signal kV R ; amplifying the difference between said stored signal V P and said reference signal V R in response to said digital output bit from the preceding cycle having said first value to generate said feedback signal having a value V C where V.sub.C =(1/(1-k)) (V.sub.P -kV.sub.R) where k has a predetermined value in the range from 0<k<1/2; and amplifying said stored signal V P in response to said digital output bit from the preceding cycle having said second value to generate said feedback signal having a value V C where V.sub.C =(1/k)V.sub.P wherein the sequential digital bits generated by said step of comparing comprises said non-binary digital word.
Claim 11
Independent Claim
356 words
A method for converting an analog signal to a corresponding non-binary digital word comprising the steps of: processing clock signals, received from an external clock, to repetitively generate a predetermined set of sequential timing signals including a first timing signal coincident with the first timing signal in each of said predetermined set of sequential timing signals; transmitting said analog signal to the output of a first switch means in response to said first timing signal and transmitting a feedback signal V c to the output of said first switch means in response to the absence of said first timing signal; transmitting by means of a second switch means the signal from the output of said first switch means to an analog storage means in response to each clock signal, to generate a stored signal V P and transmitting the stored signal V P to an output of said second switch means in the absence of said clock signal; comparing the signal at the output of said first switch means to a reference signal kV R to generate during each clock signal a digital output bit having a first value when the value of the signal at the output of said first switch means is greater than the value of said reference signal kV R and a digital output bit having a second value when the value of the signal at the output of said first switch means is less than the value of said reference signal kV R ; amplifying the difference between said stored signal V P and said reference signal V R in response to said digital output bit from the preceding cycle having said first value to generate said feedback signal having a value V C where V.sub.C =(1/(1-k)) (V.sub.P -kV.sub.R) where k has a predetermined value in the range from 0<k<1/2; and amplifying said stored signal V P in response to said digital output bit from the preceding cycle having said second value to generate said feedback signal having a value V C where V.sub.C =(1/k)V.sub.P wherein the sequential digital bits generated by said step of comparing comprises said non-binary digital word.
Claim 12
Dependent Claim
230 words
The method of claim 9 wherein said step of amplifying the difference between said stored signal V P and a reference signal V R comprises the steps of feeding back the output of a differential amplifier to it's negative input by means of a first resistance R 1 having a predetermined ohmic value; applying a reference signal V R to the negative input of said differential amplifier in response to said digital bit having said first value by means of a second resistance R 2 having an ohmic value related to the ohmic value of said first resistance R 1 in accordance with the equation R.sub.2 =((1-k)/k)R.sub.1 applying a ground signal to the negative input of said differential amplifier in response to said digital bit having said second value by means of a third resistance R 3 having an ohmic value related to the ohmic value of said first resistance R 1 in accordance with the equation: R.sub.3 =(k/(1-k))R.sub.1 applying said stored signal V P to the positive input to said differential amplifier: wherein the output of said differential amplifier is said feedback signal V C having the value, V.sub.C =(1/(1-k)) (V.sub.P -kV.sub.R) in response to applying said reference signal V R to the negative input of said differential amplifier and the value, V.sub.C =(1/k)V.sub.P in response to applying said ground signal to the negative input of said differential amplifier.
Claim 13
Dependent Claim
20 words
The method of claim 9 further including the step of converting said non-binary digital word to a corresponding digital word.
Claim 14
Dependent Claim
64 words
The method of claim 11 wherein said step of converting said non-binary word comprises the step of addressing a storage array with said non-binary word to output a corresponding binary word, said storage array containing a set of binary words, the address of each binary word being defined in terms of it's corresponding non-binary word generated in said step of converting said analog signal.
Claim 15
Dependent Claim
106 words
The method of claim 11 wherein said the relationships between the values of the ohmic values of resistances R 2 and R 3 with respect to the ohmic value of resistance R 1 differ from the desired values given by the equations R.sub.2 =((1-k)/k)R.sub.1 and R.sub.3 =(k/(1-k))R.sub.1 said method further includes the steps of: determining for each non-binary word a corresponding value for the analog signal; determining for each of said values of the analog signal a corresponding binary word; and storing said corresponding binary words in said storage array at the address locations corresponding to the non-binary words determined in said first step of determining.
Claim 16
Dependent Claim
25 words
The method of claim 12 wherein said step of addressing addresses a read only memory and wherein said read only memory is said storage array.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-31 | 1985-11-30 | 1986-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-31 | 1989-11-30 | 1990-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-31 | 1993-11-30 | 1994-06-01 | $7700.00 | Window Closed / Lapsed |