Differential-input complementary field-effect transistor amplifier

Claim 2

An FET amplifying circuit comprising: first and second input terminals for receiving input signals thereat, and an output terminal; first and second supply terminals for receiving operating potential therebetween; first, second and third FET inverter amplifier means, each having an input and an output connection and exhibiting transconductance therebetween, and having respective first and second supply connections connected to said first and second supply terminals, respectively; respective means for connecting said first and second input terminals to the input connections of said first and third inverter amplifier means, respectively; interconnection means including a first node, means for connecting the output connection of said third inverter amplifier means to said first node, means for connecting said first node to the input connection of said second inverter amplifier means, fourth FET inverter amplifier means having an input connection, and having an output connection connected to said first node and having first and second supply connections connected to said first and second supply terminals, respectively, and means for completing a degenerative feedback connection between the output and input connections of said fourth inverter amplifier means; means for combining signals including a second node, means for connecting the output connection of said first inverter amplifier means to said second node, and means for connecting the output connection of said second inverter amplifier means to said second node; and output means connecting said second node to said output terminal.

Claim 3

The circuit of claim 1 wherein each of said first, second, and third inverter amplifier means exhibits voltage gain and wherein said interconnection means includes means for reducing the voltage gain of said third inverter amplifier means to cause equal and opposite responsivity of a signal at said output terminal to the input signals at said first and second input terminals, respectively.

Claim 4

The circuit of claim 1 wherein said first and second inverter amplifier means exhibit substantially similar transconductance characteristics and wherein said third and fourth inverter amplifier means together exhibit substantially minus unity voltage gain.

Claim 5

The circuit of claim 1 wherein said second and fourth inverter amplifier means exhibit substantially similar transconductance characteristics and wherein said first and third inverter amplifier means exhibit substantially equal voltage gains.

Claim 6

The circuit of claim 1 wherein said output means includes fifth FET inverter amplifier means having an input connection to which said second node connects, having an output connection connected to said output terminal, and having first and second supply connections respectively connected to said first and second supply terminals.

Claim 7

The circuit of claim 1 further comprising: means interposed between said first supply terminal and the respective first supply connections of said first and third inverter amplifier means for varying the operating potentials applied thereto.

Claim 8

The circuit of claim 6 wherein said means for varying includes variable resistance means having respective first and second ends connected to the first supply connections of said first and third inverter amplifier means, respectively, and having a wiper arm connected to said first supply terminal.

Claim 9

The circuit of claim 6 further comprising: further means interposed between said second supply terminal and the respective second supply connections of said first and third inverter amplifying means for varying the operating potentials applied thereto.

Claim 10

The circuit of claim 8 wherein said further means for varying includes variable resistance means having respective first and second ends connected to the second supply connections of said third and first inverter amplifier means, respectively, and having a wiper arm connected to said second supply terminal.

Claim 11

The circuit of claim 8 wherein said means for varying and said further means for varying operate cooperatively so that the potentials at the first and second supply connections of said first inverter amplifier means in a first direction sense when the potentials at the first and second supply connections of said third inverter amplifier means vary in a second and opposite direction sense.

Claim 12

The circuit of claims 1 or 5 wherein each said inverter amplifier means comprises: respective first variable transconductance means for tending to decrease the conductance between the first supply and output connections thereof when the potential at the input connection thereof tends to move towards the potential at said first supply terminal, and respective second variable transconductance means for tending to decrease the conductance between the output and second supply connections thereof when the potential at the input connection tends to move towards the potential at said second supply terminal.

Claim 13

The circuit of claim 11 wherein: each said first variable transconductance means includes a first field-effect transistor of first conductivity type, having respective source and drain electrodes connected to the first supply and output connections, respectively, of said inverter amplifier means, and having a gate electrode connected to the input connection thereof; and each said second variable transconductance means includes a second field-effect transistor of complementary conductivity type, having respective drain and source electrodes connected to the output and second supply connections, respectively, of said inverter amplifier means, and having a gate electrode connected to the input connection thereof.

Claim 14

The circuit of claim 11 wherein said first and second variable transconductance means exhibit substantially similar transconductance characteristics.

Claim 15

A field-effect transistor circuit for combining signals comprising: first and second input connections to which first and second signals are applied, respectively; an output connection for supplying the combined signal therefrom; first and second field-effect transistors of N-channel and P-channel type, respectively, having respective source electrodes connected for receiving relatively negative and relatively positive potentials, respectively, and having respective gate and drain electrodes, and exhibiting respective transconductances therebetween; third and fourth field-effect transistors of N-channel and P-channel type, respectively, having respective source electrodes connected for receiving relatively negative and relatively positive potentials, respectively, and having respective gate and drain electrodes, and exhibiting respective transconductances therebetween; means for connecting said first and second transistors in inverting amplifier connection including respective means for connecting the gate electrodes of said first and second transistors, to a first node, and respective means for connecting the drain electrodes of said first and second transistors to a second node; means for connecting said third and fourth transistors in circuit including respective means for connecting the gate electrodes of said third and fourth transistors to said first node, and respective means for connecting the drain electrodes of said third and fourth transistors to said first node; means for applying current signals responsive to the signals at said first input connection to said first node; means for applying current signals responsive to the signals at said second input connection to said second node; and means connected to said second node for coupling signals responsive to the current signals thereat to said output connection.

Claim 16

A field-effect transistor circuit for combining signals comprising: first and second input connections to which first and second signals are applied, respectively; an output connection for supplying the combined signal therefrom; first and second field-effect transistors of N-channel and P-channel type, respectively, having respective source electrodes connected for receiving relatively negative and relatively positive potentials, respectively, and having respective gate and drain electrodes, and exhibiting respective transconductances therebetween; third and fourth field-effect transistors of N-channel and P-channel type, respectively, having respective source electrodes connected for receiving relatively negative and relatively positive potentials, respectively, and having respective gate and drain electrodes, and exhibiting respective transconductances therebetween; means for connecting said first and second transistors in inverting amplifier connection including respective means for connecting the gate electrodes of said first and second transistors, to a first node, and respective means for connecting the drain electrodes of said first and second transistors to a second node; means for connecting said third and fourth transistors in circuit including respective means for connecting the gate electrodes of said third and fourth transistors to said first node, and respective means for connecting the drain electrodes of said third and fourth transistors to said first node; means for applying current signals responsive to the signals at said first input connection to said first node; means for applying current signals responsive to the signals at said second input connection to said second node; and means connected to said second node for coupling signals responsive to the current signals thereat to said output connection.

Claim 17

The circuit of claim 14 wherein said first through fourth transistors exhibit transconductance characteristics for making the signal at said output connection proportionately responsive to the difference between said first and second signals.

Claim 18

The circuit of claim 14 wherein said means for applying current signals responsive to the signals at said first input connection includes first voltage-to-current converting means connected between said first input connection and said first node for supplying said current signals to said first node; and wherein said means for applying current signals responsive to the signals at said second input connection includes second voltage-to-current converting means connected between said second input connection and said second node for supplying current signals to said second node.

Claim 19

The circuit of claim 16 wherein each of said first and second voltage-to-current converting means includes: respective fifth and sixth field-effect transistors of N-channel and P-channel type, respectively, having respective source electrodes connected for receiving relatively negative and relatively positive potentials, respectively, and having respective gate and drain electrodes, and exhibiting respective transconductances therebetween; means for connecting the respective gate electrodes of said fifth and sixth transistors in common and to a respective one of said first and second input connections; and means for connecting the respective drain electrodes of said fifth and sixth transistors in common and to a respective one of said first and second nodes.

Claim 20

The circuit of claim 17 wherein said first and second transistors and the fifth and sixth transistors of said second voltage-to-current converting means exhibit substantially similar transconductance characteristics, and wherein said third and fourth transistors and the fifth and sixth transistors of said first voltage-to-current converting means exhibit transconductance characteristics for providing substantially negative unity voltage gain between said first input connection and said first node.

Claim 21

The circuit of claim 18 wherein said first through fourth transistors and the respective fifth and sixth transistors of said first and second voltage-to-current converting means exhibit substantially similar transconductance characteristics.

Claim 22

The circuit of claim 14 wherein said means for coupling signals to said output connection comprises: fifth and sixth field-effect transistors of N-channel and P-channel type, respectively, having respective source and drain and gate electrodes, the respective source electrodes of said fifth and sixth transistors receiving relatively negative and relatively positive potentials, respectively; means for respectively connecting the gate electrodes of said fifth and sixth transistors to said second node; and means for respectively connecting the drain electrodes of said fifth and sixth transistors to said output connection.

Claim 23

A field-effect transistor (FET) circuit for combining first and second signals comprising: first and second complementary FET inverter amplifier means, having respective input and output connections and exhibiting transconductance therebetween; means for connecting the output connection of said first inverter amplifier means to the input connection of said second inverter amplifier means; a direct coupled feedback connection between the output and input connections of said first inverter amplifier means; means for connecting the output connection of said second inverter amplifier means to a node; means for applying the first signal to the input connection of said first inverter amplifier means; means for applying the second signal to said node; and means connected to said node for withdrawing an output signal therefrom.

Claim 24

A field-effect transistor (FET) circuit for combining first and second signals comprising: first and second complementary FET inverter amplifier means, having respective input and output connections and exhibiting transconductance therebetween; means for connecting the output connection of said first inverter amplifier means to the input connection of said second inverter amplifier means; a direct coupled feedback connection between the output and input connections of said first inverter amplifier means; means for connecting the output connection of said second inverter amplifier means to a node; means for applying the first signal to the input connection of said first inverter amplifier means; means for applying the second signal to said node; and means connected to said node for withdrawing an output signal therefrom.

Claim 25

The circuit of claim 21 wherein the respective transconductances of said first and second inverter amplifier means are predetermined for making said output signal responsive to the difference between said first and second signals.

Claim 26

The circuit of claim 21 further including: third complementary FET inverter amplifier means included within said means for applying the first signal, having an output connection for supplying the first signal and an input connection for receiving signals to which said first signal is responsive; and fourth complementary FET inverter amplifier means including within said means for applying the second signal, having an output connection for supplying the second signal and an input connection for receiving signals to which said second signal is responsive.

Claim 27

The circuit of claim 21 or 23 wherein said means for withdrawing an output signal includes fifth complementary FET inverter amplifier means having an input connection to which said node connects, and having an output connection for supplying signals responsive to said output signal.