Patent US4331925A successfully refreshed from Google Patents.
US4331925A
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False count correction in feedback shift registers and pulse generators using feedback shift registers
Assignee: United States Department of the Army
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Filing: 1980-06-17
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Granted: 1982-05-25
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Expires: 2000-06-17
Abstract
Abstract A pulse train generator comprising a shift register with feedback for proing an output pulse for every m clock pulses applied to the shift register stages. The feedback shift register normally has a maximal length 2 n -1, where n is the number of stages. Clock pulses are applied to the shift register until an all-ONE condition is reached; thereupon, (m-1) additional clock pulses are applied and the states of the register stages can then be sensed. False count correction is obtained by the combination of a detector and an analog integrator.
Inventors
- 👤 Otto E. Rittenbach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:53
CPC Classifications
H; H01; H01Q; H01Q3/00; H01Q3/26; H01Q3/30; H01Q3/34; H01Q3/36; H01Q3/38; H01Q3/385; H03; H03K; H03K19/00; H03K19/20; H03K19/21; H03K21/00; H03K21/40; H03K23/00; H03K23/40; H03K23/50; H03K23/54
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
175 words
In combination, a feedback shift register including a plurality of cascaded bistable stages each having complementary first and second output circuits at which two distinct voltage levels may separately appear indicative of a ONE or a ZERO and having associated first and second input circuits, circuit means including a detector receptive of energy from an output circuit of one of said bistable stages and further including an integrator, said circuit means providing an output voltage which represents a ZERO during normal shifting of said shift register and providing an output voltage which is representative of a ONE when the first output circuits of all of said bistable stages remain abnormally at the voltage level indicative of a ZERO over an appreciable time interval, the output of said integrator being coupled to the first input circuit of another of said bistable stages to convert the voltage level at the first output circuit of any of said stages from a level indicative of a ZERO to a level indicative of a ONE during the aforesaid all-ZERO condition.
Claim 2
Dependent Claim
175 words
In combination, a feedback shift register including a plurality of cascaded bistable stages each having complementary first and second output circuits at which two distinct voltage levels may separately appear indicative of a ONE or a ZERO and having associated first and second input circuits, circuit means including a detector receptive of energy from an output circuit of one of said bistable stages and further including an integrator, said circuit means providing an output voltage which represents a ZERO during normal shifting of said shift register and providing an output voltage which is representative of a ONE when the first output circuits of all of said bistable stages remain abnormally at the voltage level indicative of a ZERO over an appreciable time interval, the output of said integrator being coupled to the first input circuit of another of said bistable stages to convert the voltage level at the first output circuit of any of said stages from a level indicative of a ZERO to a level indicative of a ONE during the aforesaid all-ZERO condition.
Claim 3
Dependent Claim
19 words
The combination of claim 1 wherein said circuit means includes an inverter coupled to the output of said integrator.
Claim 4
Dependent Claim
40 words
The combination of claim 1 wherein said detector includes a diode which is reverse biased when ZEROS appear at the first output circuit of said one bistable stage and further including an inverter for inverting the output of said integrator.
Claim 5
Dependent Claim
48 words
The combination of claim 1 wherein said detector includes a diode which is reverse biased when a ONE appears at the second output cirrcuit of said one bistable stage and wherein the output of said integrator is coupled to the first input circuit of any of said stages.
Claim 6
Dependent Claim
52 words
The combination of claim 1 wherein said detector includes a diode in parallel with a resistor having a resistance which is much higher than the forward resistance of said diode and considerably less than the reverse resistance of said diode and wherein said integrator is a capacitor in shunt with said detector.
Claim 7
Dependent Claim
52 words
The combination of claim 2 wherein said detector includes a diode in parallel with a resistor having a resistance which is much higher than the forward resistance of said diode and considerably less than the reverse resistance of said diode and wherein said integrator is a capacitor in shunt with said detector.
Claim 8
Dependent Claim
68 words
The combination of claim 1 wherein said shift register includes an Exclusive OR gate whose input is coupled to the last of said bistable stages and to a different one of said bistable stages and whose output is applied to an OR gate in the first input circuit of said first bistable stage, and wherein the output of said circuit means is also applied to said OR gate.
Claim 9
Dependent Claim
60 words
The combination of claim 1 wherein said shift register includes an Exclusive OR gate whose input is coupled to the last of said bistable stages and to a different one of said bistable stages and whose output is coupled to said first input circuit of said first stage, and wherein said circuit means is incorporated in said Exclusive OR gate.
Claim 10
Dependent Claim
52 words
The combination of claim 8 wherein said detector includes a diode in parallel with a resistor having a resistance which is much higher than the forward resistance of said diode and considerably less than the reverse resistance of said diode and wherein said integrator is a capacitor in shunt with said detector.
Claim 11
Dependent Claim
20 words
The combination of claim 8 wherein said first input circuit of said first stage includes only a clocked AND gate.
Claim 12
Dependent Claim
76 words
The combination of claim 1 wherein said bistable stages are receptive of clock pulses and wherein an output pulse is produced for each m clock pulses and having a pulse repetition rate greater than r/2 n -1 wherein n is the number of binary stages and r is the clock rate, and logic gating means for converting said discrete sequence to ONES in all of said first output circuits upon arrival of each mth clock pulse.
Claim 13
Dependent Claim
48 words
A pulse train generator according to claim 11 wherein said logic gating means includes an n-input AND gate which is receptive of those outputs of the n stages which contain a ONE after the (M-1)th clock pulse and an inverter in the output of said n-input AND gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-24 | 1985-11-23 | 1986-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-24 | 1989-11-23 | 1990-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-24 | 1993-11-23 | 1994-05-25 | $7700.00 | Window Closed / Lapsed |