US4329701A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor package
Assignee: JPMorgan Chase Bank NA
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Filing: 1978-03-20
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Granted: 1982-05-11
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Expires: 1998-03-20
Abstract
Abstract An improved semiconductor package is disclosed wherein a semiconductor wafer assembly includes first and second generally planar surfaces having respective first and second membrane members in overlying relationship thereto. Encompassing the periphery of the wafer assembly is a mass of retaining material, such as epoxy resin, which may overlie outer edge portions of the wafer assembly and sealingly engage the first and second membrane members. In a preferred embodiment, the semiconductor wafer assembly comprises a thyristor having a gate associated therewith having conductor means attached thereto which are embedded in a suitable layer of adhesive material which is disposed between the wafer assembly and the mass of retaining material. Another feature of the invention includes the provision of a temperature sensing element, such as a thermistor, which is disposed in intimate heat exchange relationship to the wafer assembly so as to accurately sense its operating temperature. In order to provide such heat exchange relationship, the element is preferably disposed between one of the planar surfaces of the wafer assembly and its associated membrane member, which is made to conform at least partially to the outer surface of the temperature sensing element. The element is also embedded in the aforementioned layer of adhesive material and includes signal conductor means which pass through said layer and the mass of retaining material.
Inventors
- 👤 Daniel A. Brenneman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 00:00
CPC Classifications
H; H10; H10W; H10W76/00; H10W76/10; H10W76/12; H10W76/13; H10W76/138
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
304 words
A semiconductor package comprising: a. a semiconductor wafer assembly having first and second generally planar surfaces on opposite sides thereof, said surfaces being substantially parallel to each other and of approximately equal area, the outer edge portions of said surfaces lying substantially opposite each other so as to define the periphery of said semiconductor wafer assembly, at least the central portions of said surfaces being electrically conductive and defining electrodes of said semiconductor wafer assembly; b. first and second membrane members in overlying, contiguous relationship to said respective first and second generally planar surfaces, said members being constructed of electrically conductive material; c. a mass of retaining material encompassing the periphery of said semiconductor wafer assembly and sealingly engaging outer edge portions of said first and second membrane members, said retaining material being electrically insulating whereby the edge portions of said semiconductor package are effectively sealed and electrically insulated while central portions of said first and second membrane members remain exposed for use as electrodes of said semiconductor package; and d. a temperature sensing element capable of producing an electrical signal related to its temperature, said element being disposed adjacent a peripheral portion of said wafer assembly in heat conductive relation thereto between one of said generally planar surfaces and its associated membrane member, said membrane member at least partially conforming to the shape of said element so as to be in intimate heat exchange contact therewith, whereby changes in the operating temperature of said semiconductor wafer assembly are rapidly and accurately sensed by said element; said peripheral portion being encompassed by said retaining material, and further comprising signal conductor means connected to said temperature sensing element and passing through said mass of retaining material to a point external of said package, whereby the operating temperature of said semiconductor wafer assembly may be monitored.
Claim 2
Dependent Claim
304 words
A semiconductor package comprising: a. a semiconductor wafer assembly having first and second generally planar surfaces on opposite sides thereof, said surfaces being substantially parallel to each other and of approximately equal area, the outer edge portions of said surfaces lying substantially opposite each other so as to define the periphery of said semiconductor wafer assembly, at least the central portions of said surfaces being electrically conductive and defining electrodes of said semiconductor wafer assembly; b. first and second membrane members in overlying, contiguous relationship to said respective first and second generally planar surfaces, said members being constructed of electrically conductive material; c. a mass of retaining material encompassing the periphery of said semiconductor wafer assembly and sealingly engaging outer edge portions of said first and second membrane members, said retaining material being electrically insulating whereby the edge portions of said semiconductor package are effectively sealed and electrically insulated while central portions of said first and second membrane members remain exposed for use as electrodes of said semiconductor package; and d. a temperature sensing element capable of producing an electrical signal related to its temperature, said element being disposed adjacent a peripheral portion of said wafer assembly in heat conductive relation thereto between one of said generally planar surfaces and its associated membrane member, said membrane member at least partially conforming to the shape of said element so as to be in intimate heat exchange contact therewith, whereby changes in the operating temperature of said semiconductor wafer assembly are rapidly and accurately sensed by said element; said peripheral portion being encompassed by said retaining material, and further comprising signal conductor means connected to said temperature sensing element and passing through said mass of retaining material to a point external of said package, whereby the operating temperature of said semiconductor wafer assembly may be monitored.
Claim 3
Dependent Claim
35 words
The semiconductor package of claim 1 wherein said temperature sensing element comprises a thermistor having a generally spherical shape and wherein said associated membrane member conforms to contact at least one-half of its surface area.
Claim 4
Dependent Claim
52 words
The semiconductor package of claim 1 further comprising a layer of resilient adhesive material disposed between said semiconductor wafer assembly and said mass of retaining material and at least partially surrounding said temperature sensing element, said signal conductor means being surrounded thereby at the point where said means connects to said element.
Claim 5
Dependent Claim
89 words
The semiconductor package of claim 1 wherein the outer peripheries of said semiconductor wafer assembly and said first and second membrane members are substantially circular, the diameters of said members being less than or equal to that of said semiconductor wafer assembly, said mass of retaining material overlying the outer edge portions of said first and second generally planar surfaces to form first and second cylindrical bores having their respective axes substantially perpendicular to said first and second generally planar surfaces, said bores being adapted to receive electrical conductors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-10 | 1985-11-09 | 1986-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-10 | 1989-11-09 | 1990-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-10 | 1993-11-09 | 1994-05-11 | $7700.00 | Window Closed / Lapsed |