Processor circuit for video data terminal

Claim 1

A digital processor connected between a data bus and a conventional TV set having a CRT screen and a scanning means, said TV set operating according to a raster-scan system of m lines per frame and s frames per second, said digital processor permitting the display, in the form of discrete dots having a time base for writing, on the CRT screen, a page of alphanumeric characters having an alphabet of 2 N characters, a page of characters being composed of Y rows of character cells, each row being composed of X character cells, each character cell being composed of a matrix of 1 by p dots, and a writing cursor indicating the position of the next character which is to be inscribed, said digital processor including, a ROM for decoding input instruction codes which enters said ROM, said ROM having: inputs connected to the data bus which carries said input instruction codes, and outputs; an N-bits blanking operator, said blanking operator having: N inputs connected to the data bus, N outputs and one blank command input connection; a REFRESH RAM connected for storing data representing said alphanumeric characters, said REFRESH RAM having a capacity of at least one page of X by Y words of N bits and having N data inputs connected to the N outputs of said blanking operator, and an input means for addressing said character cells, a Read/Write command input and N outputs; an N-bits latch register, said register having N inputs connected to said N outputs of said REFRESH RAM, N outputs and a load command input connection; a character ROM for generating 2 N distinct characters, said character ROM having data inputs connected to said latch register, a scanning means for scanning said character cells; the character ROM also having outputs equal in number to or less than the value L; a serializer register having inputs connected to said character ROM, a second load command input connection, a shift command input and an output connected to the TV set; a package containing a semiconductor microchip comprising the following LSI circuits: a timing generator which permits the synchronization of the TV set scanning means and of the other LSI circuits of said semiconductor microchip, this generator comprising: a clock signal source of fixed frequency which increments a first counter including a decoder which provides TV line SYNC top-signals and pulse signals for horizontal centering of the page of displayed characters and a second counter including a decoder which provides TV frame SYNC top-signals and pulse signals for vertical centering of the page of displayed characters; an address signal generator comprising: a command circuit which generates a command signal; a clock signals source which generates clock signals at a frequency equal to the time base of the dots, said clock signals source connected to the command circuit to be disabled by the command signal, the address signal generator also comprising four linked counters including decoders which are incremented by the clock signals source; these connectors being: one modulo-L counter, one modulo-X counter, one modulo-P counter, one modulo-Y counter, an output of said counter modulo-L also being connected to the shift command input of said serializer register, the output of said modulo-L counter being connected to the first load command input of said latch register and the second load command of said serializer register, the outputs of the modulo-P counter being connected to the character ROM inputs means for scanning said character cells; the command circuit of the dot clock circuit including: a first input which receives said signals for horizontal centering and a second input connected to the output of said modulo-X counter decoder, the incrementation of the modulo-P counter being enabled by said pulse signals for vertical centering; a writing address pointer with outputs connected to said REFRESH RAM, comprising an X-bits register linked through an inhibiting gate to a Y-bits register; a first multiplexer comprising a first input connected to the outputs of said writing address pointer and a second input connected to outputs of the modulo-X and modulo-Y counters and also comprising (X+Y) outputs connected to the addressing means of said REFRESH RAM, and a command input connected to receive said command signal; a decoding operator connected to said character ROM for decoding via a forcing operator means, said forcing operator means including a command input, said decoding operator being connected to generate command inputs to said writing address pointer; a writing generator connected to operate in synchronism with the TV line SYNC top-signals, said writing generator connected to the Read/Write command input of said REFRESH RAM and connected to provide an input to the writing address pointer; an erase generator for clearing an end of a row, a row, or a page of characters, said erase generator including inputs connected to said decoding operator, an output connected to the inhibiting gate of said writing address pointer, an output connected to the blank command input of said blanking operator and the command input of said forcing operators; a writing cursor generator including: a comparator of (X+Y) bits with inputs connected respectively to the outputs of said writing pointer and the outputs of said modulo-X and modulo-Y counter; and an inhibiting gate connected to receive the output of the writing cursor generator and to receive the outputs of said modulo-P counter and to generate a signal indicative thereof to the writing cursor.