High speed information selection and transfer system

Claim 1

A high speed information selection and transfer system, comprising: an information supplying unit for supplying a plurality of information units which are identified by a plurality of binary codes of n bits, respectively; a switching over unit comprising a plurality of switching elements arranged in a matrix and connected with each other between successive columns of said matrix, each element being provided with a pair of input terminals and a pair of output terminals, a connection between said pair of input terminals and a pair of output terminals in each of said switching elements being switched over between two states of parallel and crossing, and said input terminals of said switching element in the input side column of said matrix being supplied with said plurality of information units derived from said information supplying unit, respectively; a switching over commander for controlling the switching over of the states of connection in said plurality of switching elements to transfer selectively at least one of said plurality of information units from said input terminals of said switching elements in the input side column of said matrix to at least either of said pair of output terminals of at least one of said switching elements in the output side column of said matrix; said switching over commander comprising: a designated signal unit for forming a designating signal Ax, which is used for designating said switching elements to be switched over as: Ax=(a.sub.n-1 a.sub.n-2, . . . , a.sub.i, . . . , a.sub.1, a.sub.0); a buffer memory for storing said designating signal Ax in a predetermined time duration, an arithmetic unit for effecting a calculation whereby, according to a result of comparison between i-th order bits of binary codes which identify desired information to be selected out of said plurality of information units, respectively, a i =0 if all of said i-th order bits are "0", a i =1 if all of said i-th order bits are "1", and a i =x if said i-th order bits are different from each other, and a parameter b i , which represents a position of the symbol x in said designating signal Ax, being calculated by: ##EQU3## where |x| represents a number of x in said designating signal Ax, and further the switching elements in each of the columns of said matrix of said switching-over unit being identified numerically by another plurality of binary codes, respectively, a sigma calculating unit for effecting a calculation whereby the control of the switching over of the states of connection in said plurality of switching element is performed in such a manner that with respect to the switching elements in the i-th column of said matrix of said switching-over unit: if a i =0, the states of connection in the switching elements, which are numbered by the binary codes the b i -th order bits of which binary codes are "1", are switched over, if a i =1, initially, the states of connection in all of said switching elements in said i-th column of said matrix are switched over, and then the states of connection in the switching elements, which are numbered by the binary codes the b i -th order figures of which binary codes are "1", are switched over, and if a i =x, initially, the states of connection in the switching elements, which are numbered by the binary codes the n-b i -th order figures of which binary codes are "1", where the symbol z represents the value of the symbol x positioned between the terms a 0 and a z-1 of said designating signal Ax, are switched over, and then the states of connection in the switching elements, which are numbered by the binary codes the b i -th order figures of which binary codes are "1", are switched over, and a controlling signal sender for setting the state of connection of said plurality of switching elements in said switching over unit in response to the result of the calculation effected by said sigma calculating unit; and an information processing unit for processing the information units derived from said switching over unit with a plurality of input terminals which correspond in order to said output terminals of the switching elements in the output side column of the matrix.