Data processing system utilizing analog memories having different data processing characteristics

Claim 1

A data processing system in which pattern data of a predetermined standard pattern is memorized and an unknown input data is compared with the memorized pattern data to determine whether or not the unknown input data resembles the memorized pattern data comprising: clock pulse generator means for producing two phase clock pulses; a plurality of analog memory means each having different transfer characteristics, an input analog signal to be sampled and processed during a sampling period being applied simultaneously to each of said analog memory means and said two phase clock pulses from said clock pulse generator means being applied simultaneously to each of said memory means so that each of said memory means produces a single output representing said input analog signal during the sampling period; a plurality of analog switching means equal in number to the number of said analog memory means which receive the outputs of said analog memory means, respectively; a plurality of sampling hold means equal in number to the number of said analog memory means which receive output analog signals from said plurality of analog memory means through said plurality of switching means, respectively; a control means supplied with said two phase clock pulses from said clock pulse generator and producing a control signal which occurs at the end of the sampling period which is applied commonly to said plurality of analog switching means to close said analog switching means simultaneously; a plurality of analog-digital converter means equal in number to the number of said analog memory means which receive the analog output signals from said plurality of sampling hold means and convert said analog output signals into digital signals; a digital memory receiving said digital signals from said plurality of analog-digital converter means; a computer receiving the output of said digital memory; and wherein each of said analog memory means consists of a plurality of operational amplifiers, a second of plurality of switches, said plurality of operational amplifiers and second plurality of switches being alternately connected in cascade, a plurality of memory means each connected between adjacent ones of said second plurality of switches and said operational amplifiers, a plurality of taps connected to output terminals of said plurality of operational amplifiers, a plurality of resistors of different ohmic values connected to said plurality of taps, respectively, and a further operational amplifier with its input terminals connected to said resistors.