Synchronous demultiplexer with elastic bit store for TDM/PCM telecommunication system

Claim 1

A demultiplexer for an incoming bit stream organized in a succession of frames of m time slots each encompassing a group of n bits arriving over a signal path, comprising: input register means connected to said signal path for temporarily receiving successive n-bit groups; synchronization means connected to said signal path for extracting a train of first clock pulses with cycles T', corresponding to said time slots, from said incoming bit stream; a local source of second clock pulses with cycles T"≈T'; storage means with m cells accommodating respective n-bit groups and with a loading connection to said input register means; output register means linked by an unloading connection to said storage means for receiving successive n-bit groups therefrom; distributing means connected to said output register means for routing said n-bit groups to different outgoing channels; first address-generating means stepped by said first clock pulses every cycle T' for identifying a cell of said storage means in which an n-bit group present in said input register means is to be written via said loading connection; second address-generating means stepped by said second clock pulses every cycle T" for identifying a cell of said storage means from which an n-bit group is to be read out to said output register means via said unloading connection; first timing means driven by said first clock pulses for generating a series of writing commands with a recurrence period equal to a cycle T' and of a length corresponding to a minor fraction of their recurrence period; second timing means driven by said second clock pulses for generating a series of reading commands with a recurrence period equal to a cycle T" and of a length corresponding to a minor fraction of their recurrence period, one of said series of commands consisting of two interleaved sets of pulses; gating means connected to said first timing means for selectively passing pulses of either of said interleaved sets; switchover means connected to said first and second timing means for controlling said gating means to give passage to writing commands not coinciding with reading commands; and commutating means responsive to the pulses passed by said gating means and to the other of said series of commands for alternately connecting said first and second address-generating means to an address input of said storage means.