Patent US4313156A successfully refreshed from Google Patents.
US4313156A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate controlling circuit for a thyristor converter
Assignee: Toshiba Corp
•
Filing: 1979-10-05
•
Granted: 1982-01-26
•
Expires: 1999-10-05
Abstract
Abstract A gate controlling circuit for a thyristor converter having an inverse bias voltage detecting circuit which detects the inverse bias voltage across a thyristor and is connected between the anode and cathode of serially connected thyristors in a thyristor valve. A gate signal to all of the thyristors is supplied when the output of the inverse bias voltage detecting circuit drops or becomes zero after all of the thyristors are turned off.
Inventors
- 👤 Sumio Kobayashi
- 👤 Tadashi Takahashi
- 👤 Hidetoshi Ino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:45
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/08; H02M1/088; H02M1/092
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
179 words
A gate controlling circuit for a thyristor converter which has a plurality of series-connected thyristors, said circuit comprising: a reference circuit for commanding said thyristors in accordance with a predetermined sequence; first detecting means for detecting the forward bias voltage of at least one of said thyristors; second detecting means for detecting the inverse voltage of at least one of said thyristors; first logical means for generating a gate signal for the gate of said thyristors in accordance with outputs from the reference circuit and the first detecting means; second logical means for generating a gate signal for the gate of said thyristors in accordance with outputs from the reference circuit and the second detecting means, means for generating a gate signal when the output of the second logical means drops; means for adding the output of said first logical means and said means for generating a gate signal when the output of the second logical means falls; and means for generating pulses for a gate of the thyristors in accordance with the output of the means for adding.
Claim 2
Dependent Claim
179 words
A gate controlling circuit for a thyristor converter which has a plurality of series-connected thyristors, said circuit comprising: a reference circuit for commanding said thyristors in accordance with a predetermined sequence; first detecting means for detecting the forward bias voltage of at least one of said thyristors; second detecting means for detecting the inverse voltage of at least one of said thyristors; first logical means for generating a gate signal for the gate of said thyristors in accordance with outputs from the reference circuit and the first detecting means; second logical means for generating a gate signal for the gate of said thyristors in accordance with outputs from the reference circuit and the second detecting means, means for generating a gate signal when the output of the second logical means drops; means for adding the output of said first logical means and said means for generating a gate signal when the output of the second logical means falls; and means for generating pulses for a gate of the thyristors in accordance with the output of the means for adding.
Claim 3
Dependent Claim
33 words
A gate controlling circuit according to claim 1, further comprising delay means connected to the output of the means for generating a gate signal when the output of the second logical means falls.
Claim 4
Dependent Claim
17 words
A gate controlling circuit according to claim 1 wherein said means for adding is an OR gate.
Claim 5
Dependent Claim
22 words
A gate controlling circuit according to claims 1 or 2 wherein said first and said second detecting means are light emitting diodes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-01-25 | 1985-07-27 | 1986-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-01-25 | 1989-07-27 | 1990-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-01-25 | 1993-07-27 | 1994-01-26 | $7700.00 | Window Closed / Lapsed |