Coherent phase shift keyed demodulator for power line communication systems

Claim 2

A demodulator for data bit signals modulating rectangular pulse signals derived from a binary phase shift keyed carrier, comprising: means sampling said rectangular pulses and producing polarity sample bits having either of two binary logic states corresponding to first and second levels of said rectangular pulse signals with predetermined equal groups of said sample bits cyclically occurring during each data bit interval; means responsive to said predetermined equal groups of the sample bits for producing first vector component signals having a relative phase angle representation at a fundamental frequency for each separate one of said predetermined equal groups of the sample bits; means responsive to a plurality of said predetermined groups of the sample bits for producing reference vector component signals having a relative phase angle representation at said fundamental frequency; phase detector means producing correlation signals in response to phase comparisons of each of said first vector component signals and said reference vector component signals; and means selectively summing said correlation signals when produced in response to phase comparisons of said first vector component signals produced from said separate ones of said predetermined equal groups of the sample bits occurring during the same data bit intervals.

Claim 3

The demodulator as claimed in claim 1 including means responsive to said plurality of said predetermined groups of the sample bits for producing second vector component signals having a relative phase angle representation at a double carrier frequency, and means for deriving said reference vector component signals from said component signals of said second vector component signals.

Claim 4

The demodulator as claimed in claim 1 including means producing a binary coded data word signal representing the binary logic states of said sample bits included in the separate ones of said predetermined groups of the sample bits.

Claim 5

The demodulator as claimed in claim 3 wherein said means producing the data word signal includes a shift register means serially receiving said sample bits upon each occurrence thereof.

Claim 6

The demodulator as claimed in claim 3 including means having stored vector component values representing different selectable relative phase angles and further including means for selecting predetermined ones of said stored vector component values in response to each different binary coded condition of said data word signal for producing said first vector component signals.

Claim 7

The demodulator as claimed in claim 2 including means for producing a binary coded data word signal representing the binary logic states of said sample bits included in the separate ones of said predetermined groups of the sample bits, further including means having first and second stored vector component values representing different selectable relative phase angles at a fundamental frequency and at said double carrier frequency, respectively, and still further including means for concurrently selecting predetermined ones of both said first and second vector component values in response to each of different binary coded conditions of said data word signal for producing both said first vector component signals and said second vector component signals.

Claim 8

The demodulator as claimed in claim 6 including summing means for separately adding each of said vector component values together and each of said second vector values together when selected in response to a single occurrence of said data word signal for producing said first vector component signals and said second vector component signals.

Claim 9

The demodulator as claimed in claim 6 including means responsive to each adjacently opposite logic state representations in said data word signal for effecting the concurrent selections of said first and second vector component values.

Claim 10

The demodulator as claimed in claim 8 wherein each of said concurrent selections of said first and second vector component values is in response to transitions occurring between said first and second levels of said rectangular pulse signals as represented by said opposite logic state transitions.

Claim 11

The demodulator as claimed in claim 8 including first and second binary storage means wherein said first storage means serially receives said sample bits as there are produced and wherein said second storage means receives the sample bits stored in said first storage means in response to storing a complete one of said predetermined equal groups of the sample bits and further wherein said data word signal is provided by the data bits stored in said second storage means.

Claim 12

The demodulator as claimed in claim 5 wherein different binary coded conditions of said data word signal are capable of representing one and opposite transitions from the first level to the second level and from the second level to the first level, respectively, of said rectangular pulse signals, and including summing means for adding separate ones of said first vector component values derived in response to each of said one transistions with the negative of separate ones of said first vector component values derived in response to each of said opposite transitions of said rectangular pulse signals.

Claim 13

The demodulator as claimed in claim 11 wherein said first vector component values have both positive and negative weighted numerical values.

Claim 14

The demodulator as claimed in claim 1 wherein said first vector component signals and said reference vector component signals include binary representations of quadrature vector components related to a predetermined rectangular coordinate axes.

Claim 15

The demodulator as claimed in claim 1 wherein said binary phase shift keyed carrier has a predetermined frequency and a data bit rate synchronized to said carrier frequency, and further wherein said polarity samples occur at a predetermined sampling frequency with the ratio of said carrier frequency to said sampling frequency different than an integer and greater than two.

Claim 16

The demodulator as claimed in claim 14 wherein said ratio of said carrier frequency to said sampling frequency is equal to (8N±1)/8 where N is an integer.

Claim 17

The demodulator as claimed in claim 15 wherein the separate ones of said predetermined equal groups of the sample bits include at least eight of said polarity sample bits.

Claim 18

The demodulator as claimed in claim 14 wherein said predetermined carrier frequency is included in a range of approximately 9 kHz to approximately 15 kHz.

Claim 19

A demodulator for coherent phase shift keyed carrier systems wherein binary data is phase reversal keyed in a carrier having equal data bit intervals, comprising: polarity sampling means for producing binary sample signals having opposite logic states in response to the positive and negative polarity states of said carrier during each of equal segments of said carrier occurring substantially wholly within each of said data bit intervals; means for producing first relative phase angle vector signals in response to said sample signals being derived from separate ones of said carrier segments; means for producing reference phase angle vector signals in response to a said sample signals being derived from a predetermined series of the carrier segments included substantially wholly within a predetermined number of said data bit intervals; a phase detector including multiplier means for producing correlation signals responsive to a product of said first vector signals and said reference vector signals occurring with each of the separate ones of the carrier segments; means sequentially summing said correlation signals in predetermined groups including a predetermined number of the correlation signals wherein said predetermined groups correspond to a like predetermined number of the equal carrier segments; and means responsive to the sums of each of the predetermined groups of said correlation signals for producing weighted positive and negative indications thereof wherein said positive and negative indications provide corresponding binary representations effective to produce data bit signals at the output of said demodulator designating the binary information of said carrier data bits.

Claim 20

A demodulator for coherent phase shift keyed carrier systems wherein binary data is phase reversal keyed in a carrier having equal data bit intervals, comprising: polarity sampling means for producing binary sample signals having opposite logic states in response to the positive and negative polarity states of said carrier during each of equal segments of said carrier occurring substantially wholly within each of said data bit intervals; means for producing first relative phase angle vector signals in response to said sample signals being derived from separate ones of said carrier segments; means for producing reference phase angle vector signals in response to a said sample signals being derived from a predetermined series of the carrier segments included substantially wholly within a predetermined number of said data bit intervals; a phase detector including multiplier means for producing correlation signals responsive to a product of said first vector signals and said reference vector signals occurring with each of the separate ones of the carrier segments; means sequentially summing said correlation signals in predetermined groups including a predetermined number of the correlation signals wherein said predetermined groups correspond to a like predetermined number of the equal carrier segments; and means responsive to the sums of each of the predetermined groups of said correlation signals for producing weighted positive and negative indications thereof wherein said positive and negative indications provide corresponding binary representations effective to produce data bit signals at the output of said demodulator designating the binary information of said carrier data bits.

Claim 21

The demodulator as claimed in claim 18 wherein said first vector signals include two binary number values defining in-phase and quadrature components, respectively, representing a relative phase angle value of the separate carrier segments, further wherein said reference vector signals include two further binary number values defining in-phase and quadrature components, respectively, representing a phase angle value of the weighted sum average of the predetermined carrier segment series, and wherein said multiplier means separately multiplies the in-phase binary number values of said first and said reference vector signals and the quadrature phase number values of said first and said reference vector signals and adds the products of the separate multiplications to produce signed binary number values for defining said correlation signals as representing positive and negative measures of the correlation of the phase angle values of the first and relative vector signals.

Claim 22

The demodulator as claimed in claim 19 wherein the sums of said predetermined groups of the correlation signals produce corresponding signed binary number values equal to the algebraic sum values of the predetermined number of the correlation signals.

Claim 23

The demodulator as claimed in claim 18 including means for producing second relative phase angle vector signals being derived concurrently from the same carrier segments as are said first vector signals, wherein the relative phase angle values of said first and said second vector signals are representative of fundamental and second harmonic phase angle related quantities, respectively, relating to corresponding fundamental and second harmonic phase angle related quantities of said carrier.

Claim 24

The demodulator as claimed in claim 18 including means for producing second relative phase angle vector signals being concurrently derived in response to the same carrier segments as are said first vector signals, and wherein said second vector signals include two binary values defining in-phase and quadrature components, respectively, representing a second harmonic relative phase angle value, said demodulator further including digital integrator means responsive to the two binary values of said second vector signals included in said predetermined series of the carrier segments for producing two weighted sum average binary values defining in-phase and quadrature components, respectively, representing a weighted sum average second harmonic relative phase angle value, and wherein said demodulator further includes vector angle divider means for dividing said weighted sum average second harmonic relative phase angle value by two to produce said reference phase angle vector signals represented by said two binary number values wherein the binary number value of the in-phase component thereof is exclusively positive.

Claim 25

A coherent phase demodulator comprising: sampling means for producing polarity sample signals responsive to the instantaneous polarities of a received carrier signal having phase reversal keyed binary data symbols, wherein the rate of said polarity sample signals produces recurring groups thereof during each data symbol; means for deriving first phase angle signals representing a relative phase angle value for each of consecutively occurring groups of said sample signals; means for deriving reference phase angle signals representing a reference phase angle value for each of consecutive occurring predetermined numbers of said groups of sample signals; phase detector means for producing correlation signals representing the degree of positive or negative correlation of each of said first phase angle signals with each of said reference phase angle signals; signal summing means responsive to said correlation signals for producing correlation sum signals representing the algebraic sums of said correlation signals occurring during separate ones of said data symbols so as to have plus and minus numerical representations responsive to the sum values of the positive and negative correlation indications of said correlation signals; and data signal output means responsive to the summed plus or minus numerical manifestation of either the positive or the negative correlations represented by each of said correlation sum signals for generating binary data signals corresponding to the binary logic representations of said binary data symbols modulating said received carrier.

Claim 26

A coherent phase demodulator comprising: sampling means for producing polarity sample signals responsive to the instantaneous polarities of a received carrier signal having phase reversal keyed binary data symbols, wherein the rate of said polarity sample signals produces recurring groups thereof during each data symbol; means for deriving first phase angle signals representing a relative phase angle value for each of consecutively occurring groups of said sample signals; means for deriving reference phase angle signals representing a reference phase angle value for each of consecutive occurring predetermined numbers of said groups of sample signals; phase detector means for producing correlation signals representing the degree of positive or negative correlation of each of said first phase angle signals with each of said reference phase angle signals; signal summing means responsive to said correlation signals for producing correlation sum signals representing the algebraic sums of said correlation signals occurring during separate ones of said data symbols so as to have plus and minus numerical representations responsive to the sum values of the positive and negative correlation indications of said correlation signals; and data signal output means responsive to the summed plus or minus numerical manifestation of either the positive or the negative correlations represented by each of said correlation sum signals for generating binary data signals corresponding to the binary logic representations of said binary data symbols modulating said received carrier.

Claim 27

The coherent phase demodulator as claimed in claim 23 including data bit synchronization means having plural signal storage means for separately accumulating consecutively occurring continuous ones of said correlation signals from said phase detector means, said synchronization means further having counter means having the same number of counts as the number of said plural storage means for controlling the ones of said plural signal storage means to first receive one of said correlation signals and to last receive a further one of said correlation signals, and said synchronization means further having a sum signal storage means receiving the algebraic sum of said correlations in said plural signal storage means upon the last received correlation signal being received by said plural storage means, whereby said sum signal storage means provides said correlation sum signals.