US4309665A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Complementary amplifier circuit
Assignee: Hitachi Ltd
•
Filing: 1980-02-07
•
Granted: 1982-01-05
•
Expires: 2000-02-07
Abstract
Abstract A complementary amplifier circuit includes a p-channel MISFET and an n-channel MIS connected in series. The gate of the p-channel FET transistor is D.C. biased by a high impedance resistor connected between the gate and drain electrodes, and the gate of the n-channel FET is D.C. biased by a current mirror circuit formed by another n-channel FET. This complementary amplifier circuit has the advantages that the operational lower limit voltage thereof is equal to the threshold voltage of one of the MOSFETs and that stabilized operation of the amplifier is easily obtained.
Inventors
- 👤 Osamu Yamashiro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:36
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/30; H03F3/3001; G; G04; G04F; G04F5/00; G04F5/04; G04F5/06; H03B; H03B5/00; H03B5/30; H03B5/32; H03B5/36; H03B5/364; H03F3/04; H03F3/16
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
160 words
A complementary amplifier circuit comprising: first and second potential sources; a first FET of a first conductivity having a gate connected to an input terminal, a source connected to said first potential source and a drain; a second FET of a second conductivity type having a gate, a source connected to said second potential source and a drain; first connecting means connected between the drains of said first and said second FETs; bias resistive means connected between the gate and the drain of said first FET; a capacitor connected between the gates of said first and second FETs; a third FET of said second conductivity type having a gate connected to the gate of said second FET, a source connected to the source of said second FET and a drain; second connecting means connected between the drain and the gate of said third FET; and load means connected between said first potential source and the drain of the third FET.
Claim 2
Dependent Claim
160 words
A complementary amplifier circuit comprising: first and second potential sources; a first FET of a first conductivity having a gate connected to an input terminal, a source connected to said first potential source and a drain; a second FET of a second conductivity type having a gate, a source connected to said second potential source and a drain; first connecting means connected between the drains of said first and said second FETs; bias resistive means connected between the gate and the drain of said first FET; a capacitor connected between the gates of said first and second FETs; a third FET of said second conductivity type having a gate connected to the gate of said second FET, a source connected to the source of said second FET and a drain; second connecting means connected between the drain and the gate of said third FET; and load means connected between said first potential source and the drain of the third FET.
Claim 3
Dependent Claim
16 words
A complementary amplifier circuit according to claim 1, wherein said second connecting means is a resistor.
Claim 4
Dependent Claim
15 words
A complementary amplifier circuit according to claim 1, wherein said load means is a resistor.
Claim 5
Dependent Claim
48 words
A complementary amplifier circuit according to claim 1, wherein, said load means is a fourth FET of said first conductivity type having a gate, a source and a drain are connected to said second potential source, said first potential source and the drain of the third FET, respectively.
Claim 6
Dependent Claim
28 words
A complementary amplifier circuit according to claim 1, wherein said bias resistive means is constructed by complementary FETs of which the sources and the drains are commonly connected.
Claim 7
Dependent Claim
16 words
A complementary amplifier circuit according to claim 1, wherein said first connecting means includes a resistor.
Claim 8
Dependent Claim
56 words
A complementary amplifier circuit according to claim 1, wherein said first connecting means is two resistors connected in series between the drains of said first and second FETs, and further comprises a positive feedback circuit connected between the connecting point of said two resistors and the gate of said first FET and including a crystal oscillator.
Claim 9
Dependent Claim
58 words
A complementary amplifier circuit according to claims 1 or 7, further comprising a wave shaping circuit including a fourth FET of a first conductivity type, and a fifth FET of a second conductivity type complementary connected in series, the gates of said fourth and fifth FETs being connected to the drains of said first and second FETs, respectively.
References Cited (Backward Citations)
US4100502A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-01-04 | 1985-07-06 | 1986-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-01-04 | 1989-07-06 | 1990-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-01-04 | 1993-07-06 | 1994-01-05 | $7700.00 | Window Closed / Lapsed |