Patent US4308504A successfully refreshed from Google Patents.
US4308504A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Direct-coupled amplifier circuit with DC output offset regulation
Assignee: Nippon Gakki Co Ltd
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Filing: 1979-12-04
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Granted: 1981-12-29
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Expires: 1999-12-04
Abstract
Abstract A direct-coupled amplifier circuit includes an input stage differential amplifier comprised of a differential pair of field effect transistors and a pair of bipolar transistors connected in series with the differential field effect transistors, respectively and having their emitters coupled together. Gate electrodes of the differential field effect transistors are coupled to an input terminal and an output terminal of the amplifier circuit, respectively. The collector-to-emitter voltages of the bipolar transistors are controlled in accordance with the magnitude and polarity of an output DC offset voltage appearing on the output terminal so as to reduce the DC offset voltage.
Inventors
- 👤 Masaru Ida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:25
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45376
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
243 words
A direct-coupled amplifier circuit having an input terminal to receive an input signal and an output terminal to be coupled to a load, comprising: an input stage differential amplifier including a differential pair of first and second transistors each having a control electrode and first and second electrodes defining a conduction path therebetween, said control electrode of said first transistor being coupled to said input terminal and said control electrode of said second transistor being coupled to said output terminal through a negative feedback network, and third and fourth transistors having their control electrodes, first and second electrodes defining conduction paths therebetween connected in series with said conduction paths of said first and second transistors, respectively, the second electrodes of said third and fourth transistors being coupled together to a constant current source for maintaining the currents flowing in said conduction paths of said first and second transistors constant; an offset detection circuit for detecting the magnitude and polarity of an output DC offset appearing on said output terminal; and a DC offset regulation circuit for controlling only said output DC offset, said offset regulation circuit being coupled to said offset detection circuit and to the control electrodes of said third and fourth transistors for controlling voltages across said conduction paths of said third and fourth transistors as a function of the magnitude and polarity of said output DC offset detected by said offset detection circuit to thereby control said output DC offset.
Claim 2
Dependent Claim
243 words
A direct-coupled amplifier circuit having an input terminal to receive an input signal and an output terminal to be coupled to a load, comprising: an input stage differential amplifier including a differential pair of first and second transistors each having a control electrode and first and second electrodes defining a conduction path therebetween, said control electrode of said first transistor being coupled to said input terminal and said control electrode of said second transistor being coupled to said output terminal through a negative feedback network, and third and fourth transistors having their control electrodes, first and second electrodes defining conduction paths therebetween connected in series with said conduction paths of said first and second transistors, respectively, the second electrodes of said third and fourth transistors being coupled together to a constant current source for maintaining the currents flowing in said conduction paths of said first and second transistors constant; an offset detection circuit for detecting the magnitude and polarity of an output DC offset appearing on said output terminal; and a DC offset regulation circuit for controlling only said output DC offset, said offset regulation circuit being coupled to said offset detection circuit and to the control electrodes of said third and fourth transistors for controlling voltages across said conduction paths of said third and fourth transistors as a function of the magnitude and polarity of said output DC offset detected by said offset detection circuit to thereby control said output DC offset.
Claim 3
Dependent Claim
28 words
The direct-coupled amplifier circuit according to claim 1 wherein said first and second transistors are field effect transistors, and said third and fourth transistors are bipolar transistors, respectively.
Claim 4
Dependent Claim
32 words
The direct-coupled amplifier circuit according to claim 1 wherein said offset detection circuit includes a differential pair of bipolar transistors having their bases coupled to said output terminal and circuit ground, respectively.
Claim 5
Dependent Claim
75 words
The direct-coupled amplifier circuit according to claim 1 wherein said offset detection circuit includes a differential pair of fifth and sixth bipolar transistors having their bases coupled to said output terminal and circuit ground, respectively, and said offset regulation circuit includes seventh and eighth bipolar transistors having their bases coupled to collectors of said sixth and fifth bipolar transistors, respectively, and their collectors coupled to said control electrodes of said third and fourth transistors, respectively.
Claim 6
Dependent Claim
28 words
The direct-coupled amplifier circuit according to claim 1 wherein said offset detection circuit comprises capacitor means coupled between an input of an output of said offset detection circuit.
Claim 7
Dependent Claim
196 words
A direct-coupled amplifier circuit having an input terminal to receive an input signal and an output terminal to be coupled to a load, comprising: a differential amplifier including a differential pair of first and second field effect transistors each having a gate electrode, drain electrode and source electrode defining a conduction path therebetween, said gate electrode of said first field effect transistor being coupled to said input terminal and said gate electrode of said second field effect transistor being coupled to said output terminal through a negative feedback network, and third and fourth bipolar transistors having their collector-emitter paths connected in series with said conduction paths of said first and second transistors, respectively, and their emitters coupled together to a constant current source for maintaining the currents flowing in said conduction paths of said first and second field effect transistors constant; and circuit means coupled to said output terminal and to the bases of said third and fourth bipolar transistors for controlling collector-to-emitter voltages of said third and fourth bipolar transistors as a function of the magnitude and polarity of an output DC offset on said output terminal, to thereby control only said output DC offset.
Claim 8
Dependent Claim
196 words
A direct-coupled amplifier circuit having an input terminal to receive an input signal and an output terminal to be coupled to a load, comprising: a differential amplifier including a differential pair of first and second field effect transistors each having a gate electrode, drain electrode and source electrode defining a conduction path therebetween, said gate electrode of said first field effect transistor being coupled to said input terminal and said gate electrode of said second field effect transistor being coupled to said output terminal through a negative feedback network, and third and fourth bipolar transistors having their collector-emitter paths connected in series with said conduction paths of said first and second transistors, respectively, and their emitters coupled together to a constant current source for maintaining the currents flowing in said conduction paths of said first and second field effect transistors constant; and circuit means coupled to said output terminal and to the bases of said third and fourth bipolar transistors for controlling collector-to-emitter voltages of said third and fourth bipolar transistors as a function of the magnitude and polarity of an output DC offset on said output terminal, to thereby control only said output DC offset.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-12-28 | 1985-06-29 | 1985-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-12-28 | 1989-06-29 | 1989-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-12-28 | 1993-06-29 | 1993-12-29 | $7700.00 | Window Closed / Lapsed |