Patent US4308500A successfully refreshed from Google Patents.
US4308500A
Expired / Lapsed
US
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Incremental encoder for measuring positions of objects such as rotating shafts
Assignee: RCA Corp
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Filing: 1979-12-14
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Granted: 1981-12-29
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Expires: 1999-12-14
Abstract
Abstract A circuit for determining each level transition of first and second two logic level input signals and their leading or lagging phase relationship at each level transition and comprising first and second signal level storage means each having first input means responsive to the first and second input signals, respectively, first output means, and clock input means and responsive to a clock signal supplied to the clock input means to cause the logic level on its output means to become equal to the logic level on its first input means. First and second Exclusive OR gates each have a first input means connected respectively to said first input means of said first and second signal level storage means, and a second input means connected respectively to said first output means of said first and second signal level storage means. A third Exclusive OR gate responds to equal or non-equal logic levels on said first output terminal of said first Exclusive OR gate and said second input signal to produce first and second logic level, respectively. Additional means respond to the outputs of said first, second, and third Exclusive OR gates to determine the relationship of said first and second input signals at each level transition thereof and to supply a clock signal to the clock input means of said first and second signal level storage means after said additional means determines the phase relationship between said first and second input signals.
Inventors
- 👤 Jeremiah Y. Avins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:29
CPC Classifications
G; G01; G01D; G01D5/00; G01D5/12; G01D5/244; G01D5/245; G01D5/2451; G01P; G01P13/00; G01P13/02; G01P13/04; H; H03; H03M; H03M1/00; H03M1/12; H03M1/22; H03M1/24; H03M1/28; H03M1/30; Y; Y10; Y10S; Y10S177/00; Y10S177/03
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
308 words
A circuit for determining each level transition of first and second two logic level input signals and their leading or lagging phase relationship at each level transition and comprising: first and second signal level storage means each having first, second and third terminals and responsive to a clock pulse supplied to its third terminal to cause the signal logic level on its second terminal to become equal to the signal logic level on its first terminal; first and second voltage comparator means each having a first input terminal means connected respectively to said first terminal of said first and second signal level storage means, respectively, and constructed to receive, respectively, said first and second input signals, a second input terminal means connected respectively to said second terminal of said first and second signal logic level storage means, and responsive to equal or non-equal signal logic levels supplied to their first and second input terminal means to produce first and second output signal logic levels, respectively; third voltage comparator means responsive to the equality or non-equality of the signal logic level on said second terminal of said first signal level storage means and said second input signal to produce third and fourth output signal levels, respectively; clock pulse generating means for generating clock pulses; first means responsive to the output signal logic levels of said first, second, and third voltage comparator means to detect each logic level transition of said first and second input signals and the leading or lagging phase relation of said first and second input signals at each logic level transition thereof; and second means for supplying said clock pulses to said third terminal means of said first and second signal level storage means a predetermined time interval after said first means detected said leading or lagging phase relationship of said first and second input signals.
Claim 2
Dependent Claim
308 words
A circuit for determining each level transition of first and second two logic level input signals and their leading or lagging phase relationship at each level transition and comprising: first and second signal level storage means each having first, second and third terminals and responsive to a clock pulse supplied to its third terminal to cause the signal logic level on its second terminal to become equal to the signal logic level on its first terminal; first and second voltage comparator means each having a first input terminal means connected respectively to said first terminal of said first and second signal level storage means, respectively, and constructed to receive, respectively, said first and second input signals, a second input terminal means connected respectively to said second terminal of said first and second signal logic level storage means, and responsive to equal or non-equal signal logic levels supplied to their first and second input terminal means to produce first and second output signal logic levels, respectively; third voltage comparator means responsive to the equality or non-equality of the signal logic level on said second terminal of said first signal level storage means and said second input signal to produce third and fourth output signal levels, respectively; clock pulse generating means for generating clock pulses; first means responsive to the output signal logic levels of said first, second, and third voltage comparator means to detect each logic level transition of said first and second input signals and the leading or lagging phase relation of said first and second input signals at each logic level transition thereof; and second means for supplying said clock pulses to said third terminal means of said first and second signal level storage means a predetermined time interval after said first means detected said leading or lagging phase relationship of said first and second input signals.
Claim 3
Dependent Claim
55 words
A circuit as in claim 1 in which said first means comprises: bi -directional counting means responsive to said each level transition to count in first and second directions, respectively, when the output signal of said third voltage comparator means indicates, respectively, a leading or lagging phase relationship between said first and second input signals.
Claim 4
Dependent Claim
48 words
A circuit as in claim 1 wherein each of said signal level storage means is a D-type flip-flop circuit in which: said first terminal is a data (D) input terminal; said second terminal is an ouput (Q) terminal; and said third terminal is a clock pulse input terminal.
Claim 5
Dependent Claim
114 words
A circuit as in claim 1 in which: said first means comprises decoding means for producing a first train of pulses in response to each level transition of said first and second input signals when the output signal of said third voltage comparator means is at a first logic level and a second train of pulses in response to each level transition when the output signal of said third voltage comparator means is at a second logic level; in which said second means comprises logic means responsive to said first means to generate said clock pulses; and further comprising means for storing the number of pulses in said first and second trains of pulses.
Claim 6
Dependent Claim
17 words
A circuit as in claim 1 in which said first and second means comprise data processing means.
Claim 7
Dependent Claim
273 words
A circuit for detecting each level transition of first and second two-level input signals and their leading or lagging phase relationship at each level transition, and comprising: first and second signal level storage means each having a data input terminal for receiving said first and second input signals, respectively, a clock input terminal, and a first output terminal and constructed to store a signal level supplied to its data input terminal and to cause the signal level on its output terminal to become equal to the signal level on its data input terminal in response to a signal supplied to said clock input terminal; first and second Exclusive OR gate means each having a first input terminal for receiving, respectively, said first and second input signals, a second input terminal connected, respectively, to said first output terminals of said first and second signal level storage means, and a second output terminal; third Exclusive OR gate means responsive to the signal level on said first output terminal of said first signal level storage means and to said second input signal to produce an output signal indicative of the phase relationship of said first and second input signals at the last occurring level transition; first means responsive to the output signals appearing on the output terminals of said first, second and third Exclusive OR gate means to determine the phase relationship of said first and second input signal at each level transition thereof; and second means for supplying a clock pulse to said clock input terminals of said first and second level storage means after each level transition of said first and second input signals.
Claim 8
Dependent Claim
273 words
A circuit for detecting each level transition of first and second two-level input signals and their leading or lagging phase relationship at each level transition, and comprising: first and second signal level storage means each having a data input terminal for receiving said first and second input signals, respectively, a clock input terminal, and a first output terminal and constructed to store a signal level supplied to its data input terminal and to cause the signal level on its output terminal to become equal to the signal level on its data input terminal in response to a signal supplied to said clock input terminal; first and second Exclusive OR gate means each having a first input terminal for receiving, respectively, said first and second input signals, a second input terminal connected, respectively, to said first output terminals of said first and second signal level storage means, and a second output terminal; third Exclusive OR gate means responsive to the signal level on said first output terminal of said first signal level storage means and to said second input signal to produce an output signal indicative of the phase relationship of said first and second input signals at the last occurring level transition; first means responsive to the output signals appearing on the output terminals of said first, second and third Exclusive OR gate means to determine the phase relationship of said first and second input signal at each level transition thereof; and second means for supplying a clock pulse to said clock input terminals of said first and second level storage means after each level transition of said first and second input signals.
Claim 9
Dependent Claim
62 words
A circuit as in claim 6 in which said first means comprises: bi-directional counting means responsive to said each level transition of said first and second input signals to count in first and second directions, respectively, when the output signal of said third Exclusive OR gate means indicates, respectively, a leading or lagging phase relationship between said first and second input signals.
Claim 10
Dependent Claim
114 words
A circut as in claim 6 in which: said first means comprises decoding means for producing a first train of pulses in response to each level transition of said first and second input signals when the output signal of said third Exclusive OR gate means is at a first level and a second train of pulses in response to each level transition when the output signal of said third Exclusive OR gate means is at a second level: in which said second means comprises logic means responsive to said first means to generate said clock pulses; and further comprising means for storing the number of pulses in said first and second trains of pulses.
Claim 11
Dependent Claim
17 words
A circuit as in claim 6 in which said first and second means comprise data processor means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-12-28 | 1985-06-29 | 1985-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-12-28 | 1989-06-29 | 1989-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-12-28 | 1993-06-29 | 1993-12-29 | $7700.00 | Window Closed / Lapsed |