Patent US4306194A successfully refreshed from Google Patents.
US4306194A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data signal detection circuit
Assignee: International Business Machines Corp
•
Filing: 1979-10-11
•
Granted: 1981-12-15
•
Expires: 1999-10-11
Abstract
Abstract A readout signal detection circuit comprises a data signal detector which senses changes in voltage of the signal waveform relative to signal peak amplitude; a threshold detector for sensing signal peak magnitudes that exceed a preset magnitude; a differentiator to locate signal peak position; and logic circuitry to test the validity of a linear readout signal applied to the detectors and the differentiator in parallel. A ramp timer provides a delay and fixed period during which the readout signal is checked for validity.
Inventors
- 👤 Dale B. Chapman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:10
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; G11B20/10046; G11B20/10212
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
125 words
A readout signal detection circuit comprising: input means for supplying a differential linear readout signal; means coupled to said input means for detecting peak voltages of said readout signal, and changes in amplitude relative to said peak voltages; threshold detecting means coupled to said input means for sensing voltages of said readout signal; differentiator means for detecting the sign of the slopes and the occurrence of peak voltages of said readout signal, coupled to said input means; logic circuit means coupled to said threshold detecting means and said differentiator means and said peak voltage detecting means for sampling the processed readout signal to separate valid signal peaks from spurious signals; and resettable timing means for delineating the period when valid signal pulses may be passed.
Claim 2
Dependent Claim
125 words
A readout signal detection circuit comprising: input means for supplying a differential linear readout signal; means coupled to said input means for detecting peak voltages of said readout signal, and changes in amplitude relative to said peak voltages; threshold detecting means coupled to said input means for sensing voltages of said readout signal; differentiator means for detecting the sign of the slopes and the occurrence of peak voltages of said readout signal, coupled to said input means; logic circuit means coupled to said threshold detecting means and said differentiator means and said peak voltage detecting means for sampling the processed readout signal to separate valid signal peaks from spurious signals; and resettable timing means for delineating the period when valid signal pulses may be passed.
Claim 3
Dependent Claim
39 words
A readout signal detection circuit as in claim 1, including a polarity latch for storing the polarity of the last detected valid signal peak coupled to the output of said voltage change detecting means and said logic circuit means.
Claim 4
Dependent Claim
29 words
A readout signal detection circuit as in claim 2, wherein said resettable timing means comprises a ramp timer for delineating the time during which valid data pulses are passed.
Claim 5
Dependent Claim
29 words
A readout signal detecting means as in claim 3, including a ramp control latch coupled between said logic circuit means and said polarity latch for triggering said ramp timer.
Claim 6
Dependent Claim
36 words
A readout signal detection circuit as in claim 3, including an output latch responsive to said ramp timer for providing a valid output pulse at the end of the time period defined by said ramp timer.
Claim 7
Dependent Claim
23 words
A readout signal detection circuit as in claim 1, including means for setting a reference voltage coupled to said voltage change detecting means.
Claim 8
Dependent Claim
31 words
A readout signal detection circuit as in claim 1, wherein said readout signal is applied to said voltage change detecting means, said threshold detecting means and said differentiator means in parallel.
References Cited (Backward Citations)
US3437833A
Cited
US4064408A
Cited
US3631263A
Cited
US3715738A
Cited
US4163909A
Cited
US4219152A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-12-14 | 1985-06-15 | 1985-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-12-14 | 1989-06-15 | 1989-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-12-14 | 1993-06-15 | 1993-12-15 | $7700.00 | Window Closed / Lapsed |