Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
301 words
A system for reception of digital communication signals which are impressed onto a carrier in the form of binary frequency modulation and radiated through a propagation medium which is subject to reflection, particularly, for reception in mobile stations wherein unsatisfactory reception which occurs as a result of phase and amplitude distortions is automatically detected to determine their origins with two supplemental arrangements, comprising receiving means including an IF stage receiving incoming signals, an FM demodulator receiving an input from said IF stage, an AM demodulator receiving an input from said IF stage, a dynamic distortion corrector receiving the output of said FM demodulator, a polarity integrator receiving an output of said dynamic distortion corrector and an input from said AM demodulator, an AM limiter receiving an output of said AM demodulator, an inverter receiving an output of said polarity integrator and an output of said AM limiter, a data analysis circuit receiving the output of said dynamic distortion corrector and outputs from said AM limiter, said inverter, and said AM demodulator, said data analysis circuit including an FM regenerator which receives the output of said dynamic distortion corrector, a phase follow-up device including a phase comparator (Ph) which receives the output of said FM regenerator and an output from said inverter, an AM decision device including a time evaluation circuit (ZB) which receives outputs from said inverter and said AM demodulator, a bistable trigger stage (BK2) which receives the output of said time evaluation circuit ZB, a change-over switch which receives the output of said bistable trigger stage BK2, the output of said phase follow-up device, the output of said AM limiter and the output of said inverter, said change-over switch controlled by the output of said bistable trigger stage, and a data regenerator receiving the output of said change-over switch.
Claim 2
Independent Claim
301 words
A system for reception of digital communication signals which are impressed onto a carrier in the form of binary frequency modulation and radiated through a propagation medium which is subject to reflection, particularly, for reception in mobile stations wherein unsatisfactory reception which occurs as a result of phase and amplitude distortions is automatically detected to determine their origins with two supplemental arrangements, comprising receiving means including an IF stage receiving incoming signals, an FM demodulator receiving an input from said IF stage, an AM demodulator receiving an input from said IF stage, a dynamic distortion corrector receiving the output of said FM demodulator, a polarity integrator receiving an output of said dynamic distortion corrector and an input from said AM demodulator, an AM limiter receiving an output of said AM demodulator, an inverter receiving an output of said polarity integrator and an output of said AM limiter, a data analysis circuit receiving the output of said dynamic distortion corrector and outputs from said AM limiter, said inverter, and said AM demodulator, said data analysis circuit including an FM regenerator which receives the output of said dynamic distortion corrector, a phase follow-up device including a phase comparator (Ph) which receives the output of said FM regenerator and an output from said inverter, an AM decision device including a time evaluation circuit (ZB) which receives outputs from said inverter and said AM demodulator, a bistable trigger stage (BK2) which receives the output of said time evaluation circuit ZB, a change-over switch which receives the output of said bistable trigger stage BK2, the output of said phase follow-up device, the output of said AM limiter and the output of said inverter, said change-over switch controlled by the output of said bistable trigger stage, and a data regenerator receiving the output of said change-over switch.
Claim 3
Dependent Claim
137 words
A system as claimed in claim 1, wherein the time evaluation circuit includes for a time gate, a frame counter (Z1) which counts shaped pulse flanks derived from the inverter output signal and which at the end of a frame cycle emits a pulse to one input of the bistable trigger stage and to the resetting input of an event counter (Z2) which counts pulse flanks of the inverter output signal and which, when a given count is reached, emits a control pulse to the second input of the bistable trigger state, and the counting input of the event counter is preceded by an AND gate (G) which is opened by the output signal of a threshold value comparator (K) when, and only when, the AM demodulation product present at its input undershoots a given threshold value.
Claim 4
Dependent Claim
46 words
A system as claimed in claim 2, wherein the output signal of the AM decision device (14) is supplied, as a control signal, to said phase follow-up device (PE) directly, and as a switch-over signal to the change-over switch (U) indirectly through a delay element (τ1).
Claim 5
Dependent Claim
41 words
Apparatus according to claim 1 wherein said phase follow-up device includes a pair of delay means through which the outputs of said FM regenerator pass and said pair of delay means are controlled by the output of said phase comparator Ph.
Claim 6
Dependent Claim
75 words
A system as claimed in claim 4, wherein each of said delay means includes a pulse controlled shift register (SR1, SR2) which produce pulse trains derived from the FM pulse train, but which has a considerably higher pulse frequency than the FM pulse train, and output stages of the shift registers are connected, respectively to multiplexers (MUX1, MUX2) which are controlled by the phase comparator (PH) and which form a part of the delay arrangement.
Claim 7
Dependent Claim
56 words
A system as claimed in claim 5, wherein the frequency of the control pulse train for the shift registers (SR1, SR2) is four times the frequency of the FM pulse train, and the control of the delay arrangement, which consists of a shift register and a multiplexer (MUX1, MUX2) is accomplished in phase steps of ±90°.