Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
144 words
A time interval meter, comprising: a timing circuit operable at first and second predetermined rates within a predetermined timing window, said second rate being proportionately slower than said first rate; control circuit means responsive to a start signal and a stop signal for causing said timing circuit to operate at said first predetermined rate over a first time interval determined by the time difference between said start and stop signals, and for causing said timing circuit to operate at said second predetermined rate over a second time interval determined by the time difference between said stop signal and the upper limit of said predetermined timing window; means connected to said timing circuit for measuring said second time interval to provide a measured value; and means for subtracting said measured value from said predetermined timing window to provide a measurement of said first time interval.
Claim 2
Dependent Claim
144 words
A time interval meter, comprising: a timing circuit operable at first and second predetermined rates within a predetermined timing window, said second rate being proportionately slower than said first rate; control circuit means responsive to a start signal and a stop signal for causing said timing circuit to operate at said first predetermined rate over a first time interval determined by the time difference between said start and stop signals, and for causing said timing circuit to operate at said second predetermined rate over a second time interval determined by the time difference between said stop signal and the upper limit of said predetermined timing window; means connected to said timing circuit for measuring said second time interval to provide a measured value; and means for subtracting said measured value from said predetermined timing window to provide a measurement of said first time interval.
Claim 3
Dependent Claim
79 words
A time interval meter in accordance with claim 1 wherein said timing circuit comprises a capacitor and first and second constant current sources connectable to said capacitor, and wherein said control circuit means includes transistor switch means for connecting said first constant current source to said capacitor upon receipt of said start signal, and for disconnecting said first constant source from said capacitor and connecting said second constant current source to said capacitor upon receipt of said stop signal.
Claim 4
Dependent Claim
44 words
A time interval meter in accordance with claim 2 wherein said timing circuit further includes a comparator having one input thereof connected to said capacitor, and a second input thereof connected to a reference voltage to establish the upper limit of said timing window.
Claim 5
Dependent Claim
33 words
A time interval meter in accordance with claim 2 wherein said control circuit means further includes means for holding said capacitor in a predetermined state of charge until receipt of said start signal.
Claim 6
Dependent Claim
52 words
A time interval meter in accordance with claim 1 wherein said means for measuring said second time interval comprises a counter for counting clock pulses, said counter being enabled upon receipt of said interval stop signal and being disabled when said timing circuit reaches the upper limit of said predetermined timing window.
Claim 7
Dependent Claim
163 words
A circuit for measuring a time interval between a first and second event, comprising: a timing circuit including a capacitor which produces a fast ramp at a first predetermined rate and a slow ramp at a second predetermined rate between a first reference voltage and a second reference voltage, said fast ramp being initiated at said first reference voltage by said first event and being terminated at an unknown voltage between said first and second reference voltages by said second event, and said slow ramp being initiated at said unknown voltage by said second event and being terminated at said second reference voltage, the total time period between said first and second reference voltages being determined by said second predetermined rate; means connected to said timing circuit for measuring the time interval of said slow ramp; and means for subtracting the measured time interval of said slow ramp from said total time period thereby to provide the time interval of said fast ramp.
Claim 8
Dependent Claim
163 words
A circuit for measuring a time interval between a first and second event, comprising: a timing circuit including a capacitor which produces a fast ramp at a first predetermined rate and a slow ramp at a second predetermined rate between a first reference voltage and a second reference voltage, said fast ramp being initiated at said first reference voltage by said first event and being terminated at an unknown voltage between said first and second reference voltages by said second event, and said slow ramp being initiated at said unknown voltage by said second event and being terminated at said second reference voltage, the total time period between said first and second reference voltages being determined by said second predetermined rate; means connected to said timing circuit for measuring the time interval of said slow ramp; and means for subtracting the measured time interval of said slow ramp from said total time period thereby to provide the time interval of said fast ramp.
Claim 9
Dependent Claim
65 words
A circuit in accordance with claim 6 wherein said timing circuit further includes first and second constant current sources connectable to said capacitor to provide charging current therefore, and a comparator having one input thereof connected to said capacitor and a second input thereof connected to said second reference voltage, the output of said comparator being applied to said slow ramp time interval measurement means.
Claim 10
Dependent Claim
43 words
A circuit in accordance with claim 7 wherein said slow ramp time interval measurement means comprises a counter which counts clock pulses during said slow ramp time interval, said counter being enabled by said second event and being disabled by said comparator output.
Claim 11
Dependent Claim
39 words
A circuit in accordance with claim 8 further including a control circuit responsive to start and stop signals corresponding respectively to said first and second events for controlling the sequence of operation of said timing circuit and said counter.