Patent US4298947A successfully refreshed from Google Patents.
US4298947A
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Intrabox temperature display device
Assignee: Toshiba Corp
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Filing: 1979-11-15
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Granted: 1981-11-03
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Expires: 1999-11-15
Abstract
Abstract An intrabox temperature display device converts a signal representing an intrabox air temperature detected by a molded temperature sensor placed in the intrabox of a refrigerator into a digital signal by means of an A/D converter. The intrabox temperature data detected having a succession of samples with given sampling periods is stored in a memory. The intrabox temperature data read out from the memory is averaged in an operation circuit. The averaged temperature data is displayed by a display section as the temperature data approximate to a real temperature for cooling or freezing foods in the refrigerator.
Inventors
- 👤 Hiroshi Tamura
- 👤 Yutaka Nakaie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 03:57
CPC Classifications
F; F25; F25D; F25D29/00; F25D29/005; G; G01; G01K; G01K1/00; G01K1/02; G01K1/028; G01K3/00; G01K3/02; G01K3/04; F25D2400/00; F25D2400/36
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
169 words
An intrabox temperature display device comprising: a temperature sensor disposed within an intrabox for sensing a temperature of an air within the intrabox; an A/D converter for converting a signal representing the intrabox temperature detected by said temperature sensor into a digital signal; memory means comprised of n latch circuits and connected to receive clock signals from a clock signal generator in a given timing to sequentially latch n samples and store a succession of n samples each including n bits which are A/D converted by said A/D converter; an operation circuit for averaging the detected data with a succession of samples read out of said memory means to produce averaged temperature digital data; decoder means connected to said operation circuit to read out the temperature data stored at a memory location by an address signal of the averaged temperature digital data; and display means for displaying the temperature data read out of said decoder means as a temperature approximate to a temperature of a food in the intrabox.
Claim 2
Dependent Claim
169 words
An intrabox temperature display device comprising: a temperature sensor disposed within an intrabox for sensing a temperature of an air within the intrabox; an A/D converter for converting a signal representing the intrabox temperature detected by said temperature sensor into a digital signal; memory means comprised of n latch circuits and connected to receive clock signals from a clock signal generator in a given timing to sequentially latch n samples and store a succession of n samples each including n bits which are A/D converted by said A/D converter; an operation circuit for averaging the detected data with a succession of samples read out of said memory means to produce averaged temperature digital data; decoder means connected to said operation circuit to read out the temperature data stored at a memory location by an address signal of the averaged temperature digital data; and display means for displaying the temperature data read out of said decoder means as a temperature approximate to a temperature of a food in the intrabox.
Claim 3
Dependent Claim
33 words
An intrabox temperature display device according to claim 1, wherein said operation circuit sums the detected temperature information including a plurality of samples digitized and produces averaged temperature information through a bit-shift processing.
Claim 4
Dependent Claim
130 words
An intrabox temperature display device according to claim 1, wherein said operation circuit is comprised of first stage addition circuit means having a combination of a plurality adder circuits and a half adder circuit for summing corresponding output signals from latch circuits, second stage addition circuit means having a combination of a plurality of full address and a half adder circuits for summing corresponding output signals from said first stage addition circuit means, and third stage addition circuit means having a combination of a plurality of full adder circuits and half adder circuit for summing corresponding output signals from said second stage addition circuit means to produce only a given bit output signal, which is the digital data averaged of n samples inputted to said first stage addition circuit means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-11-02 | 1985-05-04 | 1985-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-11-02 | 1989-05-04 | 1989-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-11-02 | 1993-05-04 | 1993-11-03 | $7700.00 | Window Closed / Lapsed |