Data transfer system for data exchange between two operation processors

Claim 1

A data transfer system comprising: two operation processors each capable of outputting control data and address data to be transferred to the other of said two operation processors; and a pair of data transfer devices associated respectively with said two operation processors and each including addressable data memory means for storing said control data and said address data to be transferred between said two operation processors; first signal generating means connected to an associated one of said operation processors for generating a first transfer control signal during the time when said associated one of said operation processors accesses said data memory means; first access means connected between said data memory means and said associated one of said operation processors and operated in response to said first transfer control signal for transferring said control data therebetween; an address counter for outputting address data to selectively designate memory addresses of said data memory means; first and second data transmitters for transferring said control data and address data in serial fashion upon receiving the same in parallel fashion, respectively; second signal generating means connected to said first signal generating means for periodically and selectively generating second and third transfer control signals during the time when said first signal generating means is not generating said first transfer control signal; second access means connected between said address counter, said data memory means and said first and second data transmitters and operated in response to said second transfer control signal for applying said address data from said address counter to said data memory means and said second data transmitter and for applying to said first data transmitter said control data read out from said data memory means; first and second data receivers connected to said first and second data transmitters provided in the other of said data transfer devices for receiving therefrom said control data and said address data in serial fashion so as to output the same in parallel fashion, respectively; third access means connected to said first and second data receivers and said data memory means and operated in response to said third transfer control signal for storing said control data output from said first data receiver in one of said memory addresses of said data memory means designated by said address data output from said second data receiver; and counter address advancing means connected to said first and second data receivers and also connected to said address counter provided in said other data transfer device for applying a signal to increment the content of said address counter provided in said other data transfer device connected thereto each time both of said first and second data receivers complete receipt of said control data and said address data.