Patent US4297595A successfully refreshed from Google Patents.
US4297595A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal regenerating circuit with improved input-output isolation
Assignee: Wincor Nixdorf International GmbH
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Filing: 1979-06-18
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Granted: 1981-10-27
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Expires: 1999-06-18
Abstract
Abstract Digital signals are applied to an ungrounded transmission line through a two channel system, one channel being operative in response to a binary "1" the other in response to a binary "0." Each channel, when active, receives high frequency oscillations through a transformer. One side of the transformer is connected to the emitter-collector circuit of a transistor constituting a main rectifier. A buffer transistor has an emitter-collector circuit connected in series with the main rectifier transistor. A rectifier diode connected to the secondary winding of the transformer furnishes a DC signal to switch the buffer transistor to the conductive state only when high frequency oscillations appear across the secondary winding, that is when the channel is active. A high frequency filter between the main rectifier transistor and the buffer transistor prevents high frequency oscillations from reaching the output.
Inventors
- 👤 Josef Huellwegen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:57
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/0264; H04L25/0266; H04L25/0268
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
145 words
In a regenerating system for generating output signals at a system output terminal corresponding to data signals applied at a system input terminal, said system having transformer means having a primary and a secondary winding, means connected to said primary winding for applying thereto high frequency signals modulated by said data signals, main rectifier means connected to said secondary winding for rectifying said modulated high frequency signals, thereby creating first rectified signals constituting said output signals, and buffer circuit means having a high impedance and a low impedance in the absence and presence of a control signal, respectively: the improvement comprising additional rectifier means connected to said secondary winding for rectifying said modulated high frequency signals, thereby creating additional rectified signals: and connecting means for connecting said additional rectifier means to said buffer circuit means so that said additional rectified signals constitute said control signals.
Claim 2
Dependent Claim
145 words
In a regenerating system for generating output signals at a system output terminal corresponding to data signals applied at a system input terminal, said system having transformer means having a primary and a secondary winding, means connected to said primary winding for applying thereto high frequency signals modulated by said data signals, main rectifier means connected to said secondary winding for rectifying said modulated high frequency signals, thereby creating first rectified signals constituting said output signals, and buffer circuit means having a high impedance and a low impedance in the absence and presence of a control signal, respectively: the improvement comprising additional rectifier means connected to said secondary winding for rectifying said modulated high frequency signals, thereby creating additional rectified signals: and connecting means for connecting said additional rectifier means to said buffer circuit means so that said additional rectified signals constitute said control signals.
Claim 3
Dependent Claim
20 words
A system as set forth in claim 1, wherein said main rectifier means comprises the emitter-collector circuit of a transistor.
Claim 4
Dependent Claim
39 words
A system as set forth in claim 2, further comprising filter means interconnected between said main rectifier means and said system output terminal for blocking signals having a frequency exceeding a predetermined maximum frequency from said system output terminal.
Claim 5
Dependent Claim
21 words
A system as set forth in claim 3, wherein said additional rectifier means comprises a diode connected to said secondary winding.
Claim 6
Dependent Claim
19 words
A system as set forth in claim 4, further comprising a filtering circuit connected in series with said diode.
Claim 7
Dependent Claim
155 words
A system as set forth in claim 1, having a first and second system output terminal; wherein said data signals are binary signals having a first and second level; wherein said system comprises a first and second channel; wherein said transformer means comprises first and second transformer means in said first and second channel, respectively, each of said transformer means having a primary and a secondary winding; wherein said means for applying high frequency signals to said primary winding comprises means for applying high frequency signals keyed by said binary signals having said first level to said primary winding of said first transformer means and means for applying high frequency signals keyed by said binary signals having said second level to said primary winding of said second transformer means; and wherein said main rectifier means comprises first and second main rectifier means, respectively connected to said secondary winding of said first and second transformer means.
Claim 8
Dependent Claim
23 words
A system as set forth in claim 6, wherein each of said channels further comprises said additional rectifier means and said connecting means.
Claim 9
Dependent Claim
42 words
A system as set forth in claim 7, wherein said first and second channel respectively comprise first and second high frequency filter means for blocking signals having a frequency exceeding a predetermined maximum frequency from said first and second output terminal, respectively.
Claim 10
Dependent Claim
122 words
A system as set forth in claim 7, wherein said first main rectifier means and said buffer circuit means in said first channel comprise, respectively, the emitter-collector circuit of a first and second transistor; wherein said second main rectifier means and said buffer circuit means in said second channel each comprises, respectively, the emitter-collector circuit of a third and fourth transistor; further comprising means for connecting one terminal of the emitter-collector circuit of said first transistor to one terminal of said emitter-collector circuit of said third transistor, means for connecting said emitter-collector circuit of said fourth transistor in parallel with said emitter-collector circuit of said second transistor, and filter means interconnected between the so-connected first and third and second and fourth transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-26 | 1985-04-27 | 1985-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-26 | 1989-04-27 | 1989-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-26 | 1993-04-27 | 1993-10-27 | $7700.00 | Window Closed / Lapsed |