US4297591A
Expired / Lapsed
US
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Electronic counter for electrical digital pulses
Assignee: Siemens AG
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Filing: 1979-06-25
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Granted: 1981-10-27
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Expires: 1999-06-25
Abstract
Abstract An electronic counter is provided for electrical digital pulses including a counter chain comprising idential flip-flop cells to be controlled by way of a counting input by means of pulses to be counted. By means of each counting pulse given to the counting input, at least one change of the operating state of the first flip-flop cell occurs into the respectively other operating state and in which, in addition, upon a second change of the operating state of the individual flip-flop cells of the counter chain, a simultaneous change of the operating state of at least one flip-flop cell, subsequently connected to the flip-flop cell concerned or, respectively, a resetting of the operating states of all flip-flop cells of the counter chain is provided into an initial state corresponding to the counter reading ZERO. A respective transfer element is provided between two successive flip-flop cells of the counter change, which transfer element determines the counting direction and is provided with a control input to be charged by control signals. Control inputs of the transfer elements which are identical to one another are connected in common to a system which supplies the control signals. The transfer element is provided by means of transistors connected between the outputs of a flip-flop cell and the inputs of the subsequent flip-flop cell, the control electrodes of the transistors being charged by the control signals.
Inventors
- 👤 Helmut Roesler
- 👤 Otto Muehlbauer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:01
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/58
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
227 words
In a counter of the type in which a plurality of flip-flops each having a pair of inputs and a pair of outputs are provided in a chain connection and a plurality of transfer circuits are respectively interposed between successive flip-flops, the improvement wherein each of said transfer circuits comprises: a plurality of transfer transistors having conduction paths connected between the outputs of one flip-flop and the inputs of the subsequently connected flip-flop and control electrodes for receiving control signals to determine the direction of counting, said plurality of transfer transistors comprising a first field effect transistor including a source-drain path connected between a first output of a first flip-flop and a first input of a next successive, second flip-flop, and a gate connected to receive a forward count control signal; a second field effect transistor including a source-drain path connected between a second output of the first flip-flop and a second input of the second flip-flop, and a gate connected to receive the forward count control signal; a third field effect transistor including a source-drain path connected between said second output and said first input, and a gate connected to receive a backward count control signal; and a fourth field effect transistor including a source-drain path connected between said first output and said second input, and a gate connected to receive the backward count control signal.
Claim 2
Dependent Claim
227 words
In a counter of the type in which a plurality of flip-flops each having a pair of inputs and a pair of outputs are provided in a chain connection and a plurality of transfer circuits are respectively interposed between successive flip-flops, the improvement wherein each of said transfer circuits comprises: a plurality of transfer transistors having conduction paths connected between the outputs of one flip-flop and the inputs of the subsequently connected flip-flop and control electrodes for receiving control signals to determine the direction of counting, said plurality of transfer transistors comprising a first field effect transistor including a source-drain path connected between a first output of a first flip-flop and a first input of a next successive, second flip-flop, and a gate connected to receive a forward count control signal; a second field effect transistor including a source-drain path connected between a second output of the first flip-flop and a second input of the second flip-flop, and a gate connected to receive the forward count control signal; a third field effect transistor including a source-drain path connected between said second output and said first input, and a gate connected to receive a backward count control signal; and a fourth field effect transistor including a source-drain path connected between said first output and said second input, and a gate connected to receive the backward count control signal.
Claim 3
Dependent Claim
41 words
The improved counter of claim 1, further defined as each of said transfer circuits comprising: a discharge circuit connected between said first and second inputs and a reference potential, and including a control input connected to receive a discharge control signal.
Claim 4
Dependent Claim
73 words
The improved counter of claim 2, wherein said discharge circuit is defined as comprising: a first field effect discharge transistor including a source-drain path connected between said first input and the reference potential, and a gate connected to receive the discharge control signal; and a second field effect discharge transistor including a source-drain path connected between said second input and the reference potential, and a gate connected to receive the discharge control signal.
Claim 5
Dependent Claim
22 words
The improved counter of claim 3, wherein said counter, including said field effect transistors, is constructed as a monolithically integrated semiconductor circuit.
Claim 6
Dependent Claim
253 words
In a monolithic integrated semiconductor asychronous forward-backward counter in which a plurality of master-slave flip-flops each having first and second inputs and first and second outputs have transverse circuits therebetween connecting the outputs of a flip-flop to the inputs of the next successive flip-flop, the improvement wherein: each of said transfer circuits is integrated with the flip-flops and comprises a first pair of metal-oxide-semiconductor field effect transistors each including a source-drain path and a gate with said source-drain paths connected between a first output of a first flip-flop and a first input of a second, next subsequent, flip-flop, and a second output of said flip-flop and a second input of said second flip-flop, respectively, and their gates connected together to receive a forward count control signal, a second pair of metal oxide-semiconductor field effect transistors each including a source-drain path and a gate with the source-drain paths cross-connected with respect to said first pair of metal-oxide-semiconductor field effect transistors between a first output of said first flip-flop and a second input of said second flip-flop and a second output of said first flip-flop and a first input of said second flip-flop, respectively, and their gates connected together to receive a backwards count control signal, and a third pair of metal-oxide-semiconductor field effect transistors each including a source, a drain and a gate, said drains connected to respective first and second inputs of said second flip-flop, said sources connected to a reference potential and said gates connected together to receive a discharge control signal.
Claim 7
Dependent Claim
253 words
In a monolithic integrated semiconductor asychronous forward-backward counter in which a plurality of master-slave flip-flops each having first and second inputs and first and second outputs have transverse circuits therebetween connecting the outputs of a flip-flop to the inputs of the next successive flip-flop, the improvement wherein: each of said transfer circuits is integrated with the flip-flops and comprises a first pair of metal-oxide-semiconductor field effect transistors each including a source-drain path and a gate with said source-drain paths connected between a first output of a first flip-flop and a first input of a second, next subsequent, flip-flop, and a second output of said flip-flop and a second input of said second flip-flop, respectively, and their gates connected together to receive a forward count control signal, a second pair of metal oxide-semiconductor field effect transistors each including a source-drain path and a gate with the source-drain paths cross-connected with respect to said first pair of metal-oxide-semiconductor field effect transistors between a first output of said first flip-flop and a second input of said second flip-flop and a second output of said first flip-flop and a first input of said second flip-flop, respectively, and their gates connected together to receive a backwards count control signal, and a third pair of metal-oxide-semiconductor field effect transistors each including a source, a drain and a gate, said drains connected to respective first and second inputs of said second flip-flop, said sources connected to a reference potential and said gates connected together to receive a discharge control signal.
Claim 8
Dependent Claim
140 words
The improved counter of claim 5, wherein each of said flip-flops comprises: an input portion including first and second AND gates each having first and second inputs and an output, said first inputs connected together to constitute a first input of the flip-flop, first and second capacitors respectively connecting said second inputs of said AND gates to a reference potential, and first and second metal-oxide-semiconductor field effect transistors each having a source-drain path connecting said first and second outputs of said flip-flop to said first inputs of said AND gates, and commonly connected gates connected as said second input of said flip-flop; and an output portion comprising a RS flip-flop including a pair of cross-coupled gates each having an output constituting a respective output of said flip-flop and an input connected to a respective output of a respective AND gate.
Claim 9
Dependent Claim
66 words
The improved counter of claim 6, wherein said input portion further comprises third and fourth field effect transistors each having a source-drain path bridging respective capacitors and a gate connected in common to the light gate of the other to receive a common reset signal and wherein: one of said cross-coupled gates of said output portion includes a reset input connected to receive another reset signal.
Claim 10
Dependent Claim
16 words
The improved counter of claim 7, wherein: said cross-coupled gates comprise a pair of NOR gates.
Claim 11
Dependent Claim
16 words
The improved counter of claim 8, wherein all of said metal-oxide-semiconductor transistors are enhancement type transistors.
References Cited (Backward Citations)
US3277380A
Cited
US3431433A
Cited
US3295063A
Cited
US3500064A
Cited
US3745372A
Cited
US3993916A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-26 | 1985-04-27 | 1985-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-26 | 1989-04-27 | 1989-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-26 | 1993-04-27 | 1993-10-27 | $7700.00 | Window Closed / Lapsed |