Adapter unit for use in a data processing system for processing a variety of requests

Claim 2

A data processing system including a central processing unit and a controller coupled in common to a bus, said controller having a number of ports connected to a corresponding number of adapter units, one of said adapter units comprising: a data bus; an address bus; microprocessing means coupled to receive task word commands from said controller coded to specify a number of time of day operations and including time of day information signals, said microprocessing means being coupled to said data and address buses; random access memory means coupled to said data and address buses, said memory means being organized into a plurality of sections, each section having a plurality of locations, a first section corresponding to a first buffer, a second section corresponding to a second buffer, a third section corresponding to a third buffer and a fourth section corresponding to a timer control section; a programmable read only memory means coupled to said data and address buses, said read only memory means including a plurality of locations for storing a plurality of timer control sequences for processing different ones of said commands; free running time of day means for generating and storing time of day values, said time of day means being coupled to said data bus and operatively coupled to said address bus; and, timer module means coupled to said microprocessing means and to said data and address buses, said module means including a number of programmable cyclic timer circuits, each timer circuit including control and counter registers operatively coupled to said address and data buses; said microprocessing means being operative in response to one of said task commands to reference a first predetermined one of said plurality of timer control sequences for generating signals to load predetermined time of day information signals received from said controller required for executing the time of day operation specified by said command into a selected one of said buffers and for generating signals on said address and data bus lines for loading said timer control and counter registers of one of said timer circuits with control signals read out from said fourth section specifying a timer mode of operation and a predetermined time interval in accordance with said one command, said timer module means being conditioned by said control signals to generate an interrupt at the end of said predetermined time interval to said microprocessing means for detecting the completion of the time of day operation specified by said one command.

Claim 3

The system of claim 1 wherein said free running time of day means is being updated at a predetermined millisecond rate, said predetermined time of day information being coded into values representative of the year, month, day, hours and seconds and said predetermined time interval corresponding to a value no greater than said predetermined millisecond rate.

Claim 4

The system of claim 1 wherein said free running time of day means includes: a binary counter for generating a time of day value; free running clock circuit coupled to said binary counter for generating clock signals for updating said time of day value stored in said counter at a millisecond rate; an output latch register coupled to said counter and to said data bus; and decoder circuit means coupled to said data bus and to said latch register, said microprocessing means in response to said interrupt being operative to reference a predetermined one of said plurality of timer control sequences for generating signals on said address and data buses for storing in said output latch register the present time of day value read from said binary counter and for transferring said present time of day value into said first buffer for detecting said completion of said time of day operation specified by said one command.

Claim 5

The system of claim 3 wherein said one command is coded to specify a single time of day operation, said predetermined one of said plurality of timer control sequences including instructions which upon being read out from said read only memory means condition said microprocessing means to compare each of the bytes of said time of day value stored in said first buffer with a corresponding one of said bytes of the future time of day value stored in said second buffer, said microprocessing means being operative upon detecting that said present time of day value is at least equal to said future time of day value to generate signals for clearing a predetermined number of locations of said timer control section and said timer control and counter registers to zeros for processing another command specifying a time of day operation.

Claim 6

The system of claim 4 wherein said microprocessing means upon detecting that said present time of day value is less than said future time of day value is operative to generate signals for returning to a state for continuing execution of said time of day operation.

Claim 7

The system of claim 3 wherein said one command is coded to specify a repetitive time of day operation, said predetermined one of said plurality of timer control sequences including instructions which upon being read out from said read only memory means condition said microprocessing means to compare each of the bytes of said time of day value stored in said first buffer with a corresponding one of said bytes of the future time of day value stored in said second buffer, said microprocessing means being operative upon detecting said present time of day value is at least equal to said future time of day value to load a new future time of day value into said second buffer generated from the interval value stored in said third buffer and said present time of day value read from said counter for continuing the execution of said one command.

Claim 8

The system of claim 6 wherein said interval value stored in said third buffer corresponds to said predetermined information received from said controller for accurately defining successively generated intervals.

Claim 9

The system of claim 2 wherein a group of said plurality of locations of said read only memory corresponds to a task table, different ones of said group of said plurality of locations storing constant values defining which one of said plurality of timer control sequences is to be referenced to process said one command and each of said plurality of timer control sequences includes instructions containing values for defining said timer mode of operation for a selected one of said timer circuits.

Claim 10

The system of claim 8 wherein said microprocessing means in response to said one command references a first predetermined one of said group of locations of said task table to read out a first constant value specifying a single time of day operation for said timer module means and said micrprocessing means in response to said first constant value being operative to load said time of day information signals into said second buffer for subsequent comparison with time of day values obtained from said free running time of day means at intervals specified by said timer module means for detecting said completion of said time of day operation.

Claim 11

The system of claim 8 wherein said microprocessing means in response to said one command references a second predetermined one of said group of locations of said task table to read out a second constant value specifying a repetitive time of day operation for said timer module means and said microprocessing means in response to said second constant value being operative to load said time of day information signals into said third buffer and generate a future time of day value by combining said time of day information signals and a time of day value read from said interval buffer and from said free running time of day means for storage in said second buffer for subsequent comparison with time of day values obtained from said free running time of day means at intervals specified by said timer module means for detecting said completion of said time of day operation.

Claim 12

The system of claim 10 wherein said microprocessing means is operative upon detecting that one of the time of day values is at least equal to said future time of day value to generate a new time of day value by combining said time of day information signals and said one time of day values for storage in said second buffer for detecting subsequent completions of said time of day operations at intervals specified by said time of day information signals.

Claim 13

A data processing system including a central processing unit and a controller coupled in common to a bus, said controller having a number of ports connected to a corresponding number of adapter units, one of said adapter units comprising: a data bus; an address bus; microprocessing means coupled to receive task word commands from said controller coded to specify a number of time of day operations, each command including time of day information; said microprocessing means being coupled to said data and address buses; random access memory means coupled to said data and address buses, said memory means being organized into a plurality of sections, each section having a plurality of locations, a first section corresponding to a transfer buffer for storing a present time of day value, a second section corresponding to a future buffer for storing a future time of day value specifying the time for completion of said time of day operation and a third section corresponding to an interval buffer for storing a time of day interval and a fourth section corresponding to a timer control section for storing timer mode and interval signals; a programmable read only memory means coupled to said data and address buses, said memory means including a plurality of locations for storing a plurality of timer control sequences for processing different ones of said commands; free running time of day counter means for generating and storing time of day values for transfer to said transfer buffer during the execution of each command, said means being coupled to said data bus and operatively coupled to said address bus; and, timer module means coupled to said microprocessing means and to said data and address buses, said module means including a number of programmable cyclic timer circuits each including control and counter registers operatively coupled to said address and data buses, a specified one of said timer circuit control and counter registers storing signals received from said timer control section corresponding to said timer mode and interval signals; said timer module means being operative to generate an interrupt at the end of said predetermined interval to said microprocessing means and said microprocessing means being operative in response to said interrupt to compare each of the bytes of the time of day value obtained from said free running time of day means and stored in said transfer buffer with a corresponding one of said bytes of said future time of day value stored in said future buffer for detecting the completion of said time of day operation specified by the command being executed by said adapter.

Claim 14

A data processing system including a central processing unit and a controller coupled in common to a bus, said controller having a number of ports connected to a corresponding number of adapter units, one of said adapter units comprising: a data bus; an address bus; microprocessing means coupled to receive task word commands from said controller coded to specify a number of time of day operations, each command including time of day information; said microprocessing means being coupled to said data and address buses; random access memory means coupled to said data and address buses, said memory means being organized into a plurality of sections, each section having a plurality of locations, a first section corresponding to a transfer buffer for storing a present time of day value, a second section corresponding to a future buffer for storing a future time of day value specifying the time for completion of said time of day operation and a third section corresponding to an interval buffer for storing a time of day interval and a fourth section corresponding to a timer control section for storing timer mode and interval signals; a programmable read only memory means coupled to said data and address buses, said memory means including a plurality of locations for storing a plurality of timer control sequences for processing different ones of said commands; free running time of day counter means for generating and storing time of day values for transfer to said transfer buffer during the execution of each command, said means being coupled to said data bus and operatively coupled to said address bus; and, timer module means coupled to said microprocessing means and to said data and address buses, said module means including a number of programmable cyclic timer circuits each including control and counter registers operatively coupled to said address and data buses, a specified one of said timer circuit control and counter registers storing signals received from said timer control section corresponding to said timer mode and interval signals; said timer module means being operative to generate an interrupt at the end of said predetermined interval to said microprocessing means and said microprocessing means being operative in response to said interrupt to compare each of the bytes of the time of day value obtained from said free running time of day means and stored in said transfer buffer with a corresponding one of said bytes of said future time of day value stored in said future buffer for detecting the completion of said time of day operation specified by the command being executed by said adapter.

Claim 15

The system of claim 12 wherein said free running time of day counter means is being updated at a predetermined millisecond rate, said predetermined time of day information being codable into values representative of the year, month, day, hours and seconds and said predetermined time interval corresponding to a value no greater than said predetermined millisecond rate.

Claim 16

The system of claim 12 wherein said free running time of day counter means includes: a binary counter for generating a time of day value; free running clock circuit coupled to said binary counter for generating clock signals for updating said time of day value stored in said counter at a millisecond rate; an output latch register coupled to said counter and to said data bus; and decoder circuit means coupled to said data bus and to said latch register, said microprocessing means in response to said interrupt being operative to reference a predetermined one of said plurality of timer control sequences for generating signals on said address and data buses for storing in said output latch register the present time of day value read from said binary counter and for transferring said present time of day value into said transfer buffer for detecting said completion of said time of day operation specified by said one command.

Claim 17

The system of claim 14 wherein said one command is coded to specify a single time of day operation, said predetermined one of said plurality of timer control sequences including instructions which upon being read out from said read only memory means condition said microprocessing means to compare each of the bytes of said time of day value stored in said transfer buffer with a corresponding one of said bytes of the time of day value stored in said future buffer, said microprocessing means being operative upon detecting that said present time of day value is at least equal to said future time of day value to generate signals for clearing a predetermined number of locations of said timer control section and said timer control and counter registers to zeros for processing another command specifying a time of day operation.

Claim 18

The system of claim 15 wherein said microprocessing means upon detecting that said present time of day value is less than said future time of day value is operative to generate signals for returning to a state for continuing execution of said time of day operation.

Claim 19

The system of claim 14 wherein said one command is coded to specify a repetitive time of day operation, said predetermined one of said plurality of timer control sequences including instructions which upon being read out from said read only memory means condition said microprocessing means to compare each of the bytes of said time of day value stored in said transfer buffer with a corresponding one of said bytes of the time of day value stored in said future buffer, said microprocessing means being operative upon detecting said present time of day value is at least equal to said future time of day value to load a new future time of day value into said future buffer generated from the interval value stored in said interval buffer and said present time of day value read from said counter for continuing the execution of said one command.

Claim 20

The system of claim 17 wherein said interval value stored in said interval buffer corresponds to said predetermined information received from said controller for accurately defining successively generated intervals.

Claim 21

The system of claim 12 wherein a group of said plurality of locations of said read only memory corresponds to a task table, different ones of said group of said plurality of locations storing constant values defining which one of said plurality of timer control sequences is to be referenced to process said one command and each of said plurality of timer control sequences includes instructions containing values for defining said timer mode of operation for a selected one of said timer circuits.

Claim 22

The system of claim 19 wherein said microprocessing means in response to said one command references a first predetermined one of said group of locations of said task table to read out a first constant value specifying a single time of day operation for said timer module means and said microprocessing means in response to said first constant value being operative to load said time of day information signals into said future buffer for subsequent comparison with time of day values obtained from said free running time of day means at intervals specified by said timer module means for detecting said completion of said time of day operation.

Claim 23

The system of claim 19 wherein said microprocessing means in response to said one command references a second predetermined one of said group of locations of said task table to read out a second constant value specifying a repetitive time of day operation for said timer module means and said microprocessing means in response to said second constant value being operative to load said time of day information signals into said interval buffer and generate a future time of day value by combining said time of day information signals and a time of day value read from said interval buffer and said free running time of day means for storage in said future buffer for subsequent comparison with time of day values obtained from said free running time of day means at intervals specified by said timer module means for detecting said completion of said time of day operation.

Claim 24

The system of claim 21 wherein said microprocessing means is operative upon detecting that one of the time of day values is at least equal to said future time of day value to generate a new time of day value by combining said time of day information signals and said one time of day values for storage in said future buffer for detecting subsequent completions of said time of day operations at intervals specified by said time of day information signals.

Claim 25

A data processing system including a central processing unit and a controller coupled in common to a bus, said controller having a number of ports connected to a corresponding number of adapter units, one of said adapter units comprising: a microprocessing section coupled to receive commands from said controller coded to specify a number of time of day operations and including time of day values, said section including: a data bus; an address bus; microprocessing means coupled to said data and address buses; random access memory means coupled to said data and address buses, said memory means being organized into a plurality of sections, each section having a plurality of locations, a first section corresponding to a transfer buffer, a second section corresponding to a future buffer and a third section corresponding to an interval buffer and a fourth section corresponding to a timer control section; and, a programmable read only memory means coupled to said data and address buses, said memory means including a plurality of locations for storing a plurality of timer control sequences for processing different ones of said commands; a time of day counter section including: free running counter means for generating time of day values; free running clock circuit means coupled to said counter means for generating clock signals for updating said time of day values at a predetermined rate; and, output latch register means coupled to said counter means and to said data bus for storing time of day values to be transferred to said transfer buffer; timer module means coupled to said microprocessing means and to said data and address buses, said module means including a number of programmable cyclic timer circuits each including control and counter registers operatively coupled to said address and data buses; said microprocessing means being operative in response to one of said task commands to reference a first predetermined one of said plurality of timer control sequences for generating signals to load a predetermined time of day value received from said controller into a selected one of said buffers and for generating signals on said address and data bus lines for loading said timer control and counter registers of one of said timer circuits with signals read from said fourth section specifying a timer mode of operation and a predetermined time interval in accordance with said one command, said timer module means being operative to generate an interrupt at the end of said predetermined interval to said microprocessing means for detecting whether the time of day operation specified by said one command has been completed.

Claim 26

A data processing system including a central processing unit and a controller coupled in common to a bus, said controller having a number of ports connected to a corresponding number of adapter units, one of said adapter units comprising: a microprocessing section coupled to receive commands from said controller coded to specify a number of time of day operations and including time of day values, said section including: a data bus; an address bus; microprocessing means coupled to said data and address buses; random access memory means coupled to said data and address buses, said memory means being organized into a plurality of sections, each section having a plurality of locations, a first section corresponding to a transfer buffer, a second section corresponding to a future buffer and a third section corresponding to an interval buffer and a fourth section corresponding to a timer control section; and, a programmable read only memory means coupled to said data and address buses, said memory means including a plurality of locations for storing a plurality of timer control sequences for processing different ones of said commands; a time of day counter section including: free running counter means for generating time of day values; free running clock circuit means coupled to said counter means for generating clock signals for updating said time of day values at a predetermined rate; and, output latch register means coupled to said counter means and to said data bus for storing time of day values to be transferred to said transfer buffer; timer module means coupled to said microprocessing means and to said data and address buses, said module means including a number of programmable cyclic timer circuits each including control and counter registers operatively coupled to said address and data buses; said microprocessing means being operative in response to one of said task commands to reference a first predetermined one of said plurality of timer control sequences for generating signals to load a predetermined time of day value received from said controller into a selected one of said buffers and for generating signals on said address and data bus lines for loading said timer control and counter registers of one of said timer circuits with signals read from said fourth section specifying a timer mode of operation and a predetermined time interval in accordance with said one command, said timer module means being operative to generate an interrupt at the end of said predetermined interval to said microprocessing means for detecting whether the time of day operation specified by said one command has been completed.

Claim 27

The system of claim 23 wherein said predetermined rate corresponds to a one millisecond rate, said predetermined time of day information being codable into values representative of the year, month, day, hours and seconds and said predetermined time interval corresponding to a value no greater than said predetermined one millisecond rate.

Claim 28

The system of claim 24 wherein said one command is coded to specify a single time of day operation, said predetermined one of said plurality of timer control sequences including instructions which upon being read out from said read only memory means condition said microprocessing means to compare each of the bytes of said time of day value read from said time of day counter section and stored in said transfer buffer with a corresponding one of said bytes of the future time of day value stored in said future buffer, said microprocessing means being operative upon detecting that said present time of day value is at least equal to said future time of day value to generate signals for clearing a predetermined number of locations of said timer control section and said timer control and counter registers to zeroes for processing another command specifying a time of day operation.

Claim 29

The system of claim 24 wherein said one command is coded to specify a repetitive time of day operation, said predetermined one of said plurality of timer control sequences including instructions which upon being read out from said read only memory means condition said microprocessing means to compare each of the bytes of said time of day value read from said time of day counter section and stored in said transfer buffer with a corresponding one of said bytes of the time of day value stored in said future buffer, said microprocessing means being operative upon detecting said present time of day value is at least equal to said future time of day value to load a new future time of day value into said future buffer generated from the interval value stored in said interval buffer and said present time of day value read from said counter section for continuing the execution of said one command.

Claim 30

The system of claim 26 wherein said interval value stored in said interval buffer corresponds to said predetermined information received from said controller for accurately defining successively generated intervals.

Claim 31

The system of claim 23 wherein a group of said plurality of locations of said read only memory corresponds to a task table, different ones of said group of said plurality of locations storing constant values defining which one of said plurality of timer control sequences is to be referenced to process said one command and each of said plurality of timer control sequences includes instructions containing values for defining said timer mode of operation for a selected one of said timer circuits.

Claim 32

The system of claim 28 wherein said microprocessing means in response to said one command references a first predetermined one of said group of locations of said task table to read out a first constant value specifying a single time of day operation for said timer module means and said microprocessing means in response to said first constant value being operative to load said time of day information signals into said future buffer for subsequent comparison with time of day values obtained from said time of day counter section at intervals specified by said timer module means for detecting said completion of said time of day operation.

Claim 33

The system of claim 28 wherein said microprocessing means in response to said one command references a second predetermined one of said group of locations of said task table to read out a second constant value specifying a repetitive time of day operation for said timer module means and said microprocessing means in response to said second constant value being operative to load said time of day information signals into said interval buffer and generate a future time of day value by combining said time of day information signals and a time of day value read from said interval buffer and from said time of day counter section for storage in said future buffer for subsequent comparison with time of day values obtained from said time of day counter section at intervals specified by said timer module means for detecting said completion of said time of day operation.

Claim 34

The system of claim 30 wherein said microprocessing means is operative upon detecting that one of the time of day values is at least equal to said future time of day value to generate a new time of day value by combining said time of day information signals and said one time of day values for storage in said future buffer for detecting subsequent completions of said time of day operations at intervals specified by said time of day information signals.