Switched-capacitor modulator

Claim 2

A switched-capacitor modulator for modulating a carrier signal with a modulating signal to develop a modulated signal, said modulator comprising: switching means including, a first input terminal for application of the modulating signal, a second input terminal for application of a plurality of switching signals, an output terminal for providing a sampled modulating signal, a primary capacitive means having first and second plates, and a plurality of binary switches responsive to the switching signals for connecting said first and second plates to said input and output terminals; logic means responsive to the carrier signal and a clock signal having a frequency of at least four times the frequency of said carrier signal and operative to generate said switching signals; and integrator means responsive to said sampled modulating signal and operative to provide the modulated signal.

Claim 3

The modulator of claim 1 in which said plurality of binary switches includes at least a first, second, third, and fourth switch and in which said first plate is connected to said first input terminal through said first switch and to common ground through said second switch, and in which said second plate is connected to said output terminal through said third switch and to common ground through said fourth switch.

Claim 4

The modulator of claim 2 in which said logic means develops switching signals during one one-half cycle of the carrier signal which alternate with the clock signal to close said first and fourth switches and open said second and third switches to charge said primary capacitive means with the modulating signal during one one-half period of the clock signal and open said first and fourth switches and close said second and third switches to discharge said primary capacitive means during the other one-half period of the clock signal.

Claim 5

The modulator of claim 3 in which said logic means develops switching signals during the remaining one-half cycle of the carrier signal which alternate with the clock signal to close said first and third switches and open said second fourth switches to charge said primary capacitive means with the modulating signal during one one-half period of the clock signal, and to open said first and third switches and close said second and fourth switches to discharge said primary capacitive means during the other one-half period of the clock signal.

Claim 6

The modulator of claim 4 in which said modulator further includes delay means including, an operational amplifier having an input and an output terminal, a fifth switch, and a storage capacitive means, said amplifier input terminal being connected to said first input terminal through said fifth switch and said amplifier output terminal being connected to said first switch, said storage capacitive means being connected between said amplifier input terminal and common ground, said fifth switch being responsive to the switching signal activating said fourth switch.

Claim 7

The modulator of claim 3 in which said switching means further includes a fifth switch responsive to a further switching signal for connecting said first input terminal to said second plate, and in which said logic means develops said further switching signal to open said fifth switch during said one one-half cycle of the carrier signal, and in which during the remaining one-half cycle of the carrier signal said logic means develops switching signals to close said second switch and open said first and fourth switches during the duration of said remaining one-half cycle, and alternatingly to close said fifth switch and open said third switch to charge said capacitive means with the modulating signal during one one-half period of the clock signal and open said fifth switch and close said third switch to discharge said capacitive means during the other one-half period of the clock signal.

Claim 8

The modulator of claim 3 in which said switching means further includes a fifth switch responsive to a further switching signal for connecting said output terminal to said first plate, and in which said logic means develops said further switching signal to open said fifth switch during said one one-half cycle of the carrier signal, and in which during the remaining one-half cycle of the carrier signal said logic means develops switching signals to close said fourth switch and open said second and third switches during the duration of said remaining one-half cycle, and alternatingly to close said first switch and open said fifth switch to charge said capactive means with the modulating signal during one one-half period of the clock signal and open said first switch and close said fifth switch to discharge said capacitive means during the other one-half period of the clock signal.

Claim 9

The modulator of claim 5, 6, or 7 in which said switching means further includes shaping means having a plurality of secondary capacitive means and a plurality of secondary switches responsive to secondary switching signals, each secondary capacitive means being connected through one of said secondary switches across said primary capacitive means, and in which said logic means develops said secondary switching signals to activate said secondary switches at frequencies which are integer multiples of the frequency of the carrier signal.