Methods of and apparatus for generating reference voltages

Claim 2

In a system utilizing a reference voltage V, a method for providing a precise reference voltage xV comprising the steps of (a) applying said reference voltage V to one side of a first capacitor while the opposite side of said first capacitor is coupled to a point of reference potential; (b) with said opposite side of said first capacitor coupled to an input terminal of a comparator, decoupling said opposite side of said first capacitor from said point of reference potential, permitting said opposite side to "float"; (c) applying said point of reference potential to said one side of said first capacitor while said opposite side of said first capacitor remains coupled to said input terminal of said comparator; converting an output of said comparator to a nominal reference voltage xV; applying said nominal reference voltage xV to one side of a second capacitor while the opposite side of said second capacitor is coupled to said input terminal of said comparator; and (d) coupling all sides of said capacitors to said point of reference potential; and cyclically repeating the foregoing steps, wherein the ratio of the value of said first capacitor to the value of said second capacitor is x.

Claim 3

In a system utilizing a reference voltage V, a method for providing a precise reference voltage xV comprising the steps of (a) applying said reference voltage V to one side of a first capacitor while the opposite side of said first capacitor is coupled to a point of reference potential; (b) with said opposite side of said first capacitor coupled to an input terminal of a comparator, decoupling said opposite side of said first capacitor from said point of reference potential, permitting said opposite side to "float"; (c) applying said point of reference potential to said one side of said first capacitor while said opposite side of said first capacitor remains coupled to said input terminal of said comparator; converting a voltage output of said comparator to a current pulse and storing said current pulse; applying said stored pulse through a buffer to provide a nominal reference voltage xV; applying said nominal reference voltage xV to one side of a second capacitor while the opposite side of said second capacitor is coupled to said input terminal of said comparator; and (d) coupling all sides of said capacitors to said point of reference potential; and cyclically repeating the foregoing steps, wherein the ratio of the value of said first capacitor to the value of said second capacitor is x.

Claim 4

In a system utilizing a reference voltage V, a method for providing a precise reference voltage xV comprising the steps of (a) applying said reference voltage V to one side of a first capacitor while the opposite side of said first capacitor is coupled to a point of reference potential; (b) with said opposite side of said first capacitor coupled to an input terminal of a comparator, decoupling said opposite side of said first capacitor from said point of reference potential, permitting said opposite side to "float"; (c) applying said point of reference potential to said one side of said first capacitor while said opposite side of said first capacitor remains coupled to said input terminal of said comparator; converting a voltage output of said comparator to a current pulse and storing said current pulse; applying said stored pulse through a buffer to provide a nominal reference voltage xV; applying said nominal reference voltage xV to one side of a second capacitor while the opposite side of said second capacitor is coupled to said input terminal of said comparator; and (d) coupling all sides of said capacitors to said point of reference potential; and cyclically repeating the foregoing steps, wherein the ratio of the value of said first capacitor to the value of said second capacitor is x.

Claim 5

In a system utilizing a reference voltage V, a method for providing a precise reference voltage V/2 n comprising the steps of (a) applying said reference voltage V to one side of a first capacitor while the opposite side of said first capacitor is coupled to a point of reference potential; (b) with said opposite side of said first capacitor coupled to an input terminal of a comparator, decoupling said opposite side of said first capacitor from said point of reference potential, permitting said opposite side to "float"; (c) applying said point of reference potential to said one side of said first capacitor while said opposite side of said first capacitor remains coupled to said input terminal of said comparator; converting a voltage output of said comparator to a current pulse and storing said current pulse; applying said stored pulse through a buffer to provide a nominal reference voltage V/2 n ; applying said nominal reference voltage V/2 n to one side of a second capacitor while the opposite side of said second capacitor is coupled to said input terminal of said comparator; and (d) coupling all sides of said capacitors to said point of reference potential; and cyclically repeating the foregoing steps, wherein said first capacitor has a value of (2 n-1 + . . . +2 1 +2 0 ) m farads, said second capacitor has a value of (2 2n-1 + . . . +2 n ) m farads, n is a positive integer, and m is a positive constant.

Claim 6

In a system utilizing a reference voltage V, a method for providing a precise reference voltage V/2 n comprising the steps of (a) applying said reference voltage V to one side of a first capacitor while the opposite side of said first capacitor is coupled to a point of reference potential; (b) with said opposite side of said first capacitor coupled to an input terminal of a comparator, decoupling said opposite side of said first capacitor from said point of reference potential, permitting said opposite side to "float"; (c) applying said point of reference potential to said one side of said first capacitor while said opposite side of said first capacitor remains coupled to said input terminal of said comparator; converting a voltage output of said comparator to a current pulse and storing said current pulse; applying said stored pulse through a buffer to provide a nominal reference voltage V/2 n ; applying said nominal reference voltage V/2 n to one side of a second capacitor while the opposite side of said second capacitor is coupled to said input terminal of said comparator; and (d) coupling all sides of said capacitors to said point of reference potential; and cyclically repeating the foregoing steps, wherein said first capacitor has a value of (2 n-1 + . . . +2 1 +2 0 ) m farads, said second capacitor has a value of (2 2n-1 + . . . +2 n ) m farads, n is a positive integer, and m is a positive constant.

Claim 7

The method as recited in claim 3 wherein n=4, said first capacitor and said second capacitor have values of capacitance in a ratio of 15:240.

Claim 8

The method as recited in claim 4 wherein said second capacitor includes two parallel capacitive banks having a ratio of 128:112.

Claim 9

In a system providing a reference voltage +V, a method for providing precise reference voltages +V/2 n , -V/2 n , and -V, comprising the steps of (a) applying said reference voltage +V to one side of a first capacitor while the opposite side of said first capacitor is coupled to a point of reference potential; (b) with said opposite side of said first capacitor coupled to an input terminal of a comparator, decoupling said opposite side of said first capacitor from said point of reference potential, permitting said opposite side to "float"; (c) applying said point of reference potential to said one side of said first capacitor while said opposite side of said first capacitor remains coupled to said input terminal of said comparator; converting a voltage output of said comparator to a first current pulse and storing said first current pulse; applying said stored pulse through a first buffer to provide a nominal reference voltage +V/2 n ; applying said nominal reference voltage +V/2 n to one side of a second capacitor and to one side of a third capacitor while the opposite sides of said second and said third capacitors are coupled to said input terminal of said comparator; (d) coupling all sides of all said capacitors to said point of reference potential; (e) with said opposite sides of said capacitors coupled to said input terminal of said comparator, decoupling said opposite sides of said capacitors from said point of reference potential, permitting said opposite sides to "float"; (f) applying said reference voltage +V to said one side of said third capacitor while said opposite sides of said capacitors remain coupled to said input terminal of said comparator; converting a voltage output of said comparator to a second current pulse and storing said second current pulse; applying said stored second current pulse through a second buffer to provide a nominal reference voltage -V; applying said nominal reference voltage -V to said one side of said first capacitor, to said first side of said second capacitor and to one side of a fourth capacitor, an opposite side of said fourth capacitor being coupled to said input terminal of said comparator; (g) coupling all sides of all said capacitors to a point of reference potential; (h) with said opposite sides of said capacitors coupled to said input terminal of said comparator, decoupling said opposite sides of said capacitors from said point of reference potential, permitting said opposite sides to "float"; and (i) applying said reference voltage +V to said one side of said first capacitor while said opposite sides of said first capacitor remain coupled to said input terminal of said comparator; converting a voltage output of said comparator to a third current pulse and storing said third current pulse; applying said stored third current pulse through a third buffer to provide a nominal reference voltage -V/2 n ; applying said nominal reference voltage -V/2 n to said one side of said second capacitor and to said one side of said third capacitor, said one side of said fourth capacitor being coupled to said point of reference potential, wherein said first capacitor has a value of (2 n-1 + . . . +2 1 +2 0 ) m farads, said second capacitor has a value of (2 2n-2 + . . . +2 n ) m farads, said third capacitor has a value of 2 2n-1 m farads, said fourth capacitor has a value of 1 m farads, n is positive integer, and m is a positive constant.

Claim 10

In a system providing a reference voltage +V, a method for providing precise reference voltages +V/2 n , -V/2 n , and -V, comprising the steps of (a) applying said reference voltage +V to one side of a first capacitor while the opposite side of said first capacitor is coupled to a point of reference potential; (b) with said opposite side of said first capacitor coupled to an input terminal of a comparator, decoupling said opposite side of said first capacitor from said point of reference potential, permitting said opposite side to "float"; (c) applying said point of reference potential to said one side of said first capacitor while said opposite side of said first capacitor remains coupled to said input terminal of said comparator; converting a voltage output of said comparator to a first current pulse and storing said first current pulse; applying said stored pulse through a first buffer to provide a nominal reference voltage +V/2 n ; applying said nominal reference voltage +V/2 n to one side of a second capacitor and to one side of a third capacitor while the opposite sides of said second and said third capacitors are coupled to said input terminal of said comparator; (d) coupling all sides of all said capacitors to said point of reference potential; (e) with said opposite sides of said capacitors coupled to said input terminal of said comparator, decoupling said opposite sides of said capacitors from said point of reference potential, permitting said opposite sides to "float"; (f) applying said reference voltage +V to said one side of said third capacitor while said opposite sides of said capacitors remain coupled to said input terminal of said comparator; converting a voltage output of said comparator to a second current pulse and storing said second current pulse; applying said stored second current pulse through a second buffer to provide a nominal reference voltage -V; applying said nominal reference voltage -V to said one side of said first capacitor, to said first side of said second capacitor and to one side of a fourth capacitor, an opposite side of said fourth capacitor being coupled to said input terminal of said comparator; (g) coupling all sides of all said capacitors to a point of reference potential; (h) with said opposite sides of said capacitors coupled to said input terminal of said comparator, decoupling said opposite sides of said capacitors from said point of reference potential, permitting said opposite sides to "float"; and (i) applying said reference voltage +V to said one side of said first capacitor while said opposite sides of said first capacitor remain coupled to said input terminal of said comparator; converting a voltage output of said comparator to a third current pulse and storing said third current pulse; applying said stored third current pulse through a third buffer to provide a nominal reference voltage -V/2 n ; applying said nominal reference voltage -V/2 n to said one side of said second capacitor and to said one side of said third capacitor, said one side of said fourth capacitor being coupled to said point of reference potential, wherein said first capacitor has a value of (2 n-1 + . . . +2 1 +2 0 ) m farads, said second capacitor has a value of (2 2n-2 + . . . +2 n ) m farads, said third capacitor has a value of 2 2n-1 m farads, said fourth capacitor has a value of 1 m farads, n is positive integer, and m is a positive constant.

Claim 11

The method as recited in claim 6 wherein n=4, said first capacitor, said second capacitor, said third capacitor, and said fourth capacitor have values of capacitance in proportion of 15, 112, 128, and 1, respectively.

Claim 12

The method as recited in claim 6 wherein said steps are cyclically repeated.

Claim 13

The method as recited in claim 6 wherein said steps (a), (b), (c), (d), (e), (f), (g), (h), and (i) are cyclically repeated.

Claim 14

The method as recited in claim 6 wherein said steps (a), (b), (c), (g), (h), (i), (d), (e), and (f) are performed in repeated sequential order.

Claim 15

In a system utilizing a reference voltage V, a method for providing a precise reference voltage V/2 n comprising the steps of (a) applying said reference voltage V to one side of a first capacitor while the opposite side of said first capacitor is coupled to a point of reference potential; (b) with said opposite side of said first capacitor coupled to an input terminal of a comparator, decoupling said opposite side of said first capacitor from said point of reference potential, permitting said opposite side to "float"; (c) applying said point of reference potential to said one side of said first capacitor while said opposite side of said first capacitor remains coupled to said input terminal of said comparator; storing an output of said comparator; applying said stored output through a voltage divider to provide a nominal reference voltage V/2 n ;applying said nominal reference voltage V/2 n to one side of a second capacitor while the opposite side of said second capacitor is coupled to said input terminal of said comparator; and (d) coupling all sides of said capacitors to said point of reference potential; and cyclically repeating the foregoing steps, wherein said first capacitor has a value of (2 n-1 + . . . +2 1 +2 0 ) m farads, said second capacitor has a value of (2 2n-1 + . . . +2 n ) m farads, n is a positive integer, and m is a positive constant.

Claim 16

In a system utilizing a reference voltage V, a method for providing a precise reference voltage V/2 n comprising the steps of (a) applying said reference voltage V to one side of a first capacitor while the opposite side of said first capacitor is coupled to a point of reference potential; (b) with said opposite side of said first capacitor coupled to an input terminal of a comparator, decoupling said opposite side of said first capacitor from said point of reference potential, permitting said opposite side to "float"; (c) applying said point of reference potential to said one side of said first capacitor while said opposite side of said first capacitor remains coupled to said input terminal of said comparator; storing an output of said comparator; applying said stored output through a voltage divider to provide a nominal reference voltage V/2 n ;applying said nominal reference voltage V/2 n to one side of a second capacitor while the opposite side of said second capacitor is coupled to said input terminal of said comparator; and (d) coupling all sides of said capacitors to said point of reference potential; and cyclically repeating the foregoing steps, wherein said first capacitor has a value of (2 n-1 + . . . +2 1 +2 0 ) m farads, said second capacitor has a value of (2 2n-1 + . . . +2 n ) m farads, n is a positive integer, and m is a positive constant.

Claim 17

The method as recited in claim 11 wherein n=4, said first capacitor and said second capacitor have values of capacitance in a ratio of 15:240.

Claim 18

The method as recited in claim 12 wherein said second capacitor includes two parallel capacitive banks having a ratio of 128:112.

Claim 19

In a system utilizing a reference voltage +V, a method for providing precise reference voltages +V/2 n , -V/2 n , and -V, comprising the steps of (a) applying said reference voltage +V to one side of a first capacitor while the opposite side of said first capacitor is coupled to a point of reference potential; (b) with said opposite side of said first capacitor coupled to an input terminal of a comparator, decoupling said opposite side of said first capacitor from said point of reference potential, permitting said opposite side to "float"; (c) applying said point of reference potential to said one side of said first capacitor while said opposite side of said first capacitor remains coupled to said input terminal of said comparator; storing a first output of said comparator; applying said first stored output through a first voltage divider to provide a nominal reference voltage +V/2 n ; applying said nominal reference voltage +V/2 n to one side of a second capacitor and to one side of a third capacitor while the opposite sides of said second and said third capacitors are coupled to said input terminal of said comparator; (d) coupling all sides of all said capacitors to said point of reference potential; (e) with said opposite sides of said capacitors coupled to said input terminal of said comparator, decoupling said opposite sides of said capacitors from said point of reference potential, permitting said opposite sides to "float"; (f) applying said reference voltage +V to said one side of said third capacitor while said opposite sides of said capacitors remain coupled to said input terminal of said comparator; storing a second output of said comparator; applying said stored second output through a second voltage divider to provide a nominal reference voltage -V; applying said nominal reference voltage -V to said one side of said first capacitor, to said first side of said second capacitor and to one side of a fourth capacitor, an opposite side of said fourth capacitor being coupled to said input terminal of said comparator; (g) coupling all sides of all said capacitors to a point of reference potential; (h) with said opposite sides of said capacitors coupled to said input terminal of said comparator, decoupling said opposite sides of said capacitors from said point of reference potential, permitting said opposite sides to "float"; and (i) applying said reference voltage +V to said one side of said first capacitor while said opposite sides of said first capacitor remain coupled to said input terminal of said comparator; storing a third output of said comparator; applying said stored third output through a third voltage divider to provide a nominal reference voltage -V/2 n ; applying said nominal reference voltage -V/2 n to said one side of said second capacitor and to said one side of said third capacitor, said one side of said fourth capacitor being coupled to said point of reference potential, wherein said first capacitor has a value of (2 n-1 + . . . +2 1 +2 0 ) m farads, said second capacitor has a value of (2 2n-2 + . . . +2 n ) m farads, said third capacitor has a value of 2 2n-1 m farads, said fourth capacitor has a value of 1 m farads, n is a positive integer, and m is a positive constant.

Claim 20

In a system utilizing a reference voltage +V, a method for providing precise reference voltages +V/2 n , -V/2 n , and -V, comprising the steps of (a) applying said reference voltage +V to one side of a first capacitor while the opposite side of said first capacitor is coupled to a point of reference potential; (b) with said opposite side of said first capacitor coupled to an input terminal of a comparator, decoupling said opposite side of said first capacitor from said point of reference potential, permitting said opposite side to "float"; (c) applying said point of reference potential to said one side of said first capacitor while said opposite side of said first capacitor remains coupled to said input terminal of said comparator; storing a first output of said comparator; applying said first stored output through a first voltage divider to provide a nominal reference voltage +V/2 n ; applying said nominal reference voltage +V/2 n to one side of a second capacitor and to one side of a third capacitor while the opposite sides of said second and said third capacitors are coupled to said input terminal of said comparator; (d) coupling all sides of all said capacitors to said point of reference potential; (e) with said opposite sides of said capacitors coupled to said input terminal of said comparator, decoupling said opposite sides of said capacitors from said point of reference potential, permitting said opposite sides to "float"; (f) applying said reference voltage +V to said one side of said third capacitor while said opposite sides of said capacitors remain coupled to said input terminal of said comparator; storing a second output of said comparator; applying said stored second output through a second voltage divider to provide a nominal reference voltage -V; applying said nominal reference voltage -V to said one side of said first capacitor, to said first side of said second capacitor and to one side of a fourth capacitor, an opposite side of said fourth capacitor being coupled to said input terminal of said comparator; (g) coupling all sides of all said capacitors to a point of reference potential; (h) with said opposite sides of said capacitors coupled to said input terminal of said comparator, decoupling said opposite sides of said capacitors from said point of reference potential, permitting said opposite sides to "float"; and (i) applying said reference voltage +V to said one side of said first capacitor while said opposite sides of said first capacitor remain coupled to said input terminal of said comparator; storing a third output of said comparator; applying said stored third output through a third voltage divider to provide a nominal reference voltage -V/2 n ; applying said nominal reference voltage -V/2 n to said one side of said second capacitor and to said one side of said third capacitor, said one side of said fourth capacitor being coupled to said point of reference potential, wherein said first capacitor has a value of (2 n-1 + . . . +2 1 +2 0 ) m farads, said second capacitor has a value of (2 2n-2 + . . . +2 n ) m farads, said third capacitor has a value of 2 2n-1 m farads, said fourth capacitor has a value of 1 m farads, n is a positive integer, and m is a positive constant.

Claim 21

The method as recited in claim 14 wherein n=4, said first capacitor, said second capacitor, said third capacitor, and said fourth capacitor have values of capacitance in proportion of 15, 112, 128, and 1, respectively.

Claim 22

The method as recited in claim 14 wherein said steps are cyclically repeated.

Claim 23

The method as recited in claim 14 wherein said steps (a), (b), (c), (d), (e), (f), (g), (h), and (i) are cyclically repeated.

Claim 24

The method as recited in claim 14 wherein said steps (a), (b), (c), (g), (h), (i), (d), (e), and (f) are performed in repeated sequential order.

Claim 25

Apparatus, utilizing a reference voltage V, for providing a precise reference voltage xV comprising (a) a comparator having an input terminal and an output terminal; (b) a first capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; (c) means for applying said reference voltage V to said first terminal of said first capacitor while said second terminal of said first capacitor is coupled to a point of reference potential; (d) means for decoupling said second terminal from said point of reference potential; (e) a voltage-to-current pulse converter having an output, and having an input coupled to said output terminal of said comparator; (f) a storage capacitor coupled across said point of reference potential and said output of said converter; (g) a buffer having an output, and having an input coupled to said output of said converter; (h) a second capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; and (i) means for applying said output of said buffer to said first terminal of said second capacitor, wherein the ratio of the value of said first capacitor to the value of said second capacitor is x.

Claim 26

Apparatus, utilizing a reference voltage V, for providing a precise reference voltage xV comprising (a) a comparator having an input terminal and an output terminal; (b) a first capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; (c) means for applying said reference voltage V to said first terminal of said first capacitor while said second terminal of said first capacitor is coupled to a point of reference potential; (d) means for decoupling said second terminal from said point of reference potential; (e) a voltage-to-current pulse converter having an output, and having an input coupled to said output terminal of said comparator; (f) a storage capacitor coupled across said point of reference potential and said output of said converter; (g) a buffer having an output, and having an input coupled to said output of said converter; (h) a second capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; and (i) means for applying said output of said buffer to said first terminal of said second capacitor, wherein the ratio of the value of said first capacitor to the value of said second capacitor is x.

Claim 27

Apparatus, utilizing a reference voltage V, for providing a precise reference voltage xV comprising (a) a comparator having an input terminal and an output terminal; (b) a first capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; (c) means for applying said reference voltage V to said first terminal of said first capacitor while said second terminal of said first capacitor is coupled to a point of reference potential; (d) means for decoupling said second terminal from said point of reference potential; (e) a capacitive attenuator/memory coupled to said output terminal of said comparator; (f) a voltage divider controlled by said capacitive attenuator/memory; (g) a second capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; and (h) means for applying an output of said voltage divider to said first terminal of said second capacitor, wherein the ratio of the value of said first capacitor to the value of said second capacitor is x.

Claim 28

Apparatus, utilizing a reference voltage V, for providing a precise reference voltage xV comprising (a) a comparator having an input terminal and an output terminal; (b) a first capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; (c) means for applying said reference voltage V to said first terminal of said first capacitor while said second terminal of said first capacitor is coupled to a point of reference potential; (d) means for decoupling said second terminal from said point of reference potential; (e) a capacitive attenuator/memory coupled to said output terminal of said comparator; (f) a voltage divider controlled by said capacitive attenuator/memory; (g) a second capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; and (h) means for applying an output of said voltage divider to said first terminal of said second capacitor, wherein the ratio of the value of said first capacitor to the value of said second capacitor is x.

Claim 29

Apparatus, utilizing a reference voltage V, for providing a precise reference voltage V/2 n comprising (a) a comparator having an input terminal and an output terminal; (b) a first capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; (c) means for applying said reference voltage V to said first terminal of said first capacitor while said second terminal of said first capacitor is coupled to a point of reference potential; (d) means for decoupling said second terminal from said point of reference potential; (e) a voltage-to-current pulse converter having an output, and having an input coupled to said output terminal of said comparator; (f) a storage capacitor coupled across said point of reference potential and said output of said converter; (g) a buffer having an output, and having an input coupled to said output of said converter; (h) a second capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; and (i) means for applying said output of said buffer to said first terminal of said second capacitor, wherein said first capacitor has a value of (2 n-1 + . . . +2 1 +2 0 ) m farads, said second capacitor has a value of (2 2n-1 + . . . +2 n ) m farads, n is a positive integer, and m is a positive constant.

Claim 30

Apparatus, utilizing a reference voltage V, for providing a precise reference voltage V/2 n comprising (a) a comparator having an input terminal and an output terminal; (b) a first capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; (c) means for applying said reference voltage V to said first terminal of said first capacitor while said second terminal of said first capacitor is coupled to a point of reference potential; (d) means for decoupling said second terminal from said point of reference potential; (e) a voltage-to-current pulse converter having an output, and having an input coupled to said output terminal of said comparator; (f) a storage capacitor coupled across said point of reference potential and said output of said converter; (g) a buffer having an output, and having an input coupled to said output of said converter; (h) a second capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; and (i) means for applying said output of said buffer to said first terminal of said second capacitor, wherein said first capacitor has a value of (2 n-1 + . . . +2 1 +2 0 ) m farads, said second capacitor has a value of (2 2n-1 + . . . +2 n ) m farads, n is a positive integer, and m is a positive constant.

Claim 31

The apparatus as recited in claim 21 wherein n=4, and said first capacitor and said second capacitor have values of capacitance in a ratio of 15:240.

Claim 32

The apparatus as recited in claim 22 wherein said second capacitor includes two capacitive banks having a ratio of 128:112.

Claim 33

The apparatus as recited in claim 23 further comprising (j) a second voltage-to-current pulse converter having an output, and having an input coupled to said output terminal of said comparator; (k) a third voltage-to-current pulse converter having an output, and having an input coupled to said output terminal of said comparator; (l) a second storage capacitor coupled across said point of reference potential and said output of said second converter; (m) a third storage capacitor coupled across said point of reference potential and said output of said third converter; (n) a second buffer having an output, and having an input coupled to said output of said second converter; (o) a third buffer having an output, and having an input coupled to said output of said third converter; (p) means for applying said output of said second buffer to said first terminal of said first capacitor and to one only of said capacitive banks; and (q) means for applying said output of said third buffer to said first terminal of said second capacitor.

Claim 34

The apparatus as recited in claim 24 wherein said first capacitor and said capacitive banks have values of 15, 112, 128 m farads, respectively.

Claim 35

The apparatus as recited in claim 25 further comprising a fourth capacitor having a value of 1 m farads coupled between said input of said comparator and, selectively, either a point of reference potential or a reference voltage -V.

Claim 36

Apparatus, utilizing a reference voltage V, for providing a precise reference voltage V/2 n comprising (a) a comparator having an input terminal and an output terminal; (b) a first capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; (c) means for applying said reference voltage V to said first terminal of said first capacitor while said second terminal of said first capacitor is coupled to a point of reference potential; (d) means for decoupling said second terminal from said point of reference potential; (e) a capacitive attenuator/memory having an input coupled to said output terminal of said comparator; (f) a voltage divider controlled by said capacitive attenuator/memory; (g) a second capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; and (h) means for applying an output of said voltage divider to said first terminal of said second capacitor, wherein said first capacitor has a value of (2 n-1 + . . . +2 1 +2 0 ) m farads, said second capacitor has a value of (2 2n-1 + . . . +2 n ) m farads, n is a positive integer, and m is a positive constant.

Claim 37

Apparatus, utilizing a reference voltage V, for providing a precise reference voltage V/2 n comprising (a) a comparator having an input terminal and an output terminal; (b) a first capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; (c) means for applying said reference voltage V to said first terminal of said first capacitor while said second terminal of said first capacitor is coupled to a point of reference potential; (d) means for decoupling said second terminal from said point of reference potential; (e) a capacitive attenuator/memory having an input coupled to said output terminal of said comparator; (f) a voltage divider controlled by said capacitive attenuator/memory; (g) a second capacitor having a first terminal, and a second terminal coupled to said input terminal of said comparator; and (h) means for applying an output of said voltage divider to said first terminal of said second capacitor, wherein said first capacitor has a value of (2 n-1 + . . . +2 1 +2 0 ) m farads, said second capacitor has a value of (2 2n-1 + . . . +2 n ) m farads, n is a positive integer, and m is a positive constant.

Claim 38

The apparatus as recited in claim 27 wherein n=4, and said first capacitor and said second capacitor have values of capacitance in a ratio of 15:240.

Claim 39

The apparatus as recited in claim 28 wherein said second capacitor includes two capacitive banks having a ratio of 128:112.

Claim 40

The apparatus as recited in claim 29 further comprising (i) a second capacitive attenuator/memory having an output, and having an input coupled to said output terminal of said comparator; (j) a third capacitive attenuator/memory having an output, and having an input coupled to said output terminal of said comparator; (k) a second voltage divider controlled by said second capacitive attenuator/memory; (l) a third voltage divider controlled by said third capacitive attenuator/memory; (m) means for applying an output of said second voltage divider to said first terminal of said first capacitor and to one only of said capacitive banks; and (n) means for applying an output of said third voltage divider to said first terminal of said second capacitor.

Claim 41

The apparatus as recited in claim 30 wherein said first capacitor and said capacitive banks have values of 15, 112, 128 m farads, respectively.

Claim 42

The apparatus as recited in claim 31 further comprising a fourth capacitor having a value of 1 m farads coupled between said input of said comparator and, selectively, either a point of reference potential or a reference voltage -V.