US4295059A
Expired / Lapsed
US
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High gain latching Darlington transistor
Assignee: General Electric Co
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Filing: 1979-03-30
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Granted: 1981-10-13
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Expires: 1999-03-30
Abstract
Abstract A high gain latching Darlington transistor comprises a gate turn-off thyristor and a load transistor coupled in Darlington configuration. Circuit means including a diode are coupled to the gate turn-off thyristor and the transistor to provide a low loss path for load transistor current which reverse biases the gate-cathode junction of the thyristor at thyristor turn-off to prevent premature device conduction. The latching Darlington transistor configured in this manner thus operates as a conventional gate turn-off thyristor, capable of being pulsed into and out of conduction, but yet exhibits improved dv/dt capability and increased turn-off gain, typically between 10 and 100 times the turn-off gain of the individual gate turn-off thyristor.
Inventors
- 👤 Robert L. Steigerwald
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:42
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/72; H03K17/73; H03K17/567
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
141 words
A high gain latching Darlington transistor having increased dv/dt capability comprising: (a) a four-layer PNPN semiconductor switching device having a gate, a cathode, and an anode electrode, said four-layer PNPN semiconductor switching device conducting current through the anode-cathode portion thereof in accordance with the polarity of the gating pulse signals applied to said gate electrode; (b) a load transistor having a base, a collector, and an emitter electrode, said load transistor coupled in Darlington configuration to said four-layer PNPN semiconductor switching device, said load transistor conducting substantial load current through the collector-emitter portion thereof in response to current conduction through said four-layer PNPN semiconductor switching device; and (c) first and second diodes coupled in inverse series aiding fashion between the gate electrode of said 4-layer PNPN semiconductor and the junction of said 4-layer PNPN semiconductor and said load transistor base electrode.
Claim 2
Dependent Claim
141 words
A high gain latching Darlington transistor having increased dv/dt capability comprising: (a) a four-layer PNPN semiconductor switching device having a gate, a cathode, and an anode electrode, said four-layer PNPN semiconductor switching device conducting current through the anode-cathode portion thereof in accordance with the polarity of the gating pulse signals applied to said gate electrode; (b) a load transistor having a base, a collector, and an emitter electrode, said load transistor coupled in Darlington configuration to said four-layer PNPN semiconductor switching device, said load transistor conducting substantial load current through the collector-emitter portion thereof in response to current conduction through said four-layer PNPN semiconductor switching device; and (c) first and second diodes coupled in inverse series aiding fashion between the gate electrode of said 4-layer PNPN semiconductor and the junction of said 4-layer PNPN semiconductor and said load transistor base electrode.
Claim 3
Dependent Claim
27 words
The invention according to claim 1 wherein said four-layer PNPN semiconductor switching device comprises a conventional gate turn-off thyristor and said load transistor comprises an NPN transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-12 | 1985-04-13 | 1985-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-12 | 1989-04-13 | 1989-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-12 | 1993-04-13 | 1993-10-13 | $7700.00 | Window Closed / Lapsed |