Patent US4293822A successfully refreshed from Google Patents.
US4293822A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gated AGC amplifier with dc feedback
Assignee: Lockheed Martin Corp
•
Filing: 1979-11-09
•
Granted: 1981-10-06
•
Expires: 1999-11-09
Abstract
Abstract A gated multiple stage AGC amplifier circuit comprising a differentially connected transistor pair in each stage and employing a dc feedback network for maintaining a balanced current conduction in the transistors of each transistor pair for achieving maximum gain and dynamic range throughout the gated operation. The dc feedback network includes a bias capacitor, a dc bus coupling a dc bias voltage across the capacitor to each transistor pair, and bias control means responsive to transistor current conduction for supplying charge and discharge currents that are made equal to each other for maintaining a stable dc bias voltage across said bias capacitor that results in said balanced current conduction, said bias control means exhibiting impedance characteristics that maintain said stable bias voltage throughout the gated amplifier operation. The invention has particular application to the receiver of a pulse echo system wherein the amplifier is gated "on" to correspond with received echo pulses.
Inventors
- 👤 Robert J. McFadyen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:22
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/3052; H03G3/3073; H03G3/3005
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
184 words
An amplifier circuit in the form of a cascade arrangement of amplification stages each including a differentially connected pair of first and second transistors, said circuit comprising: (a) an input stage, at least one intermediate stage, and an output stage, (b) input means for applying an ac input signal to the first transistor of said input stage, (c) dc feedback means including an ac bypass capacitor across which is established a dc bias voltage and a dc bus coupling the dc bias voltage across said capacitor to the second transistor of each stage of said amplifier circuit for providing optimum amplifier gain characteristics, (d) said dc feedback means further including bias control means having a first current path responsive to current flowing in the first transistor of said output stage for providing charge current to said capacitor, and a second current path responsive to current flowing in the second transistor of said output stage for providing discharge current for said capacitor, the voltage across said capacitor being substantially constant when said charge and discharge currents are equal for establishing a stable dc bias condition.
Claim 2
Dependent Claim
184 words
An amplifier circuit in the form of a cascade arrangement of amplification stages each including a differentially connected pair of first and second transistors, said circuit comprising: (a) an input stage, at least one intermediate stage, and an output stage, (b) input means for applying an ac input signal to the first transistor of said input stage, (c) dc feedback means including an ac bypass capacitor across which is established a dc bias voltage and a dc bus coupling the dc bias voltage across said capacitor to the second transistor of each stage of said amplifier circuit for providing optimum amplifier gain characteristics, (d) said dc feedback means further including bias control means having a first current path responsive to current flowing in the first transistor of said output stage for providing charge current to said capacitor, and a second current path responsive to current flowing in the second transistor of said output stage for providing discharge current for said capacitor, the voltage across said capacitor being substantially constant when said charge and discharge currents are equal for establishing a stable dc bias condition.
Claim 3
Dependent Claim
55 words
An amplifier circuit as in claim 1 that is normally operated in a gated "on-off" mode in which said bias control means is constructed to be a current source means for said capacitor during periods when said amplifier circuit is gated "on" and a high impedance during periods when said amplifier circuit is gated "off".
Claim 4
Dependent Claim
120 words
An amplifier circuit as in claim 2 in which said first current path includes a first current mirror semiconductor means coupled to the first transistor of said output stage so as to conduct current substantially equal to current flowing in said first transistor and in a given direction with respect to said capacitor, and said second current path includes a second current mirror semiconductor means coupled through an auxiliary current path of said dc feedback means to the second transistor of said output stage so as to conduct current substantially equal to current flowing in said auxiliary current path and in said second transistor and in a direction opposite to that of said given direction with respect to said capacitor.
Claim 5
Dependent Claim
43 words
An amplifier circuit as in claim 3 in which said auxiliary current path includes a third current mirror semiconductor means coupled to the second transistor of said output stage so as to conduct current substantially equal to current flowing in said second transistor.
Claim 6
Dependent Claim
40 words
An amplifier circuit as in claim 4 in which said auxiliary current path includes a further transistor coupled in cascode with said third semiconductor means so that substantially equal voltages can be established across said first and third semiconductor means.
Claim 7
Dependent Claim
39 words
An amplifier circuit as in claim 5 in which said second semiconductor means is coupled in a Wilson circuit arrangement with respect to said auxiliary current path so that the proper voltage conditions can be established across said capacitor.
Claim 8
Dependent Claim
19 words
An amplifier circuit as in claim 6 in which said first, second and third semiconductor means comprise transistor devices.
Claim 9
Dependent Claim
32 words
An amplifier circuit as in claim 7 in which the differentially connected pair of transistors of said amplification stages are connected to current source transistors for controlling the transconductance of each stage.
Claim 10
Dependent Claim
65 words
An amplifier circuit as in claim 8 further comprising: (a) AGC control means for coupling an AGC signal to said current source transistors for controlling the transconductance of each stage as a function of said AGC signal, and (b) gate control means for applying a gate control signal for gating "on-off" said current source transistors and thereby controlling the gated operation of said amplifier circuit.
Claim 11
Dependent Claim
44 words
An amplifier circuit as in claim 9 in which said input and intermediate stages have single ended output connections and said final stage has a balanced circuit configuration and a differential output connection providing the input to a final amplification stage of constant gain.
Claim 12
Dependent Claim
174 words
An amplifier circuit in the form of a cascade arrangement of amplification stages each including a differentially connected pair of first and second transistors, said circuit comprising: (a) an input stage and at least one other stage, (b) input means for applying an ac input signal to the base of the first transistor of said input stage, (c) a dc bus coupled to the base of the second transistor of each stage of said amplifier circuit, (d) a capacitor coupled to said dc bus for providing a virtual ac ground to the base of each second transistor, said signal creating an ac imbalance between the first and second transistor of each stage, and (e) dc feedback means coupled to said dc bus comprising bias control means for simultaneously charging and discharging said capacitor by currents respectively responsive to the currents flowing in said first and second transistors of said other stage, said charging and discharging currents being in a sense to achieve dc balance between the first and second transistors of said amplification stages.
Claim 13
Dependent Claim
174 words
An amplifier circuit in the form of a cascade arrangement of amplification stages each including a differentially connected pair of first and second transistors, said circuit comprising: (a) an input stage and at least one other stage, (b) input means for applying an ac input signal to the base of the first transistor of said input stage, (c) a dc bus coupled to the base of the second transistor of each stage of said amplifier circuit, (d) a capacitor coupled to said dc bus for providing a virtual ac ground to the base of each second transistor, said signal creating an ac imbalance between the first and second transistor of each stage, and (e) dc feedback means coupled to said dc bus comprising bias control means for simultaneously charging and discharging said capacitor by currents respectively responsive to the currents flowing in said first and second transistors of said other stage, said charging and discharging currents being in a sense to achieve dc balance between the first and second transistors of said amplification stages.
Claim 14
Dependent Claim
84 words
An amplifier circuit as in claim 11 which is normally operated in a gated "on-off" mode in which said bias control means includes a current source and a current sink for respectively charging and discharging said capacitor during periods when said amplifier circuit is gated "on", said current source and said current sink having a high impedance, zero current condition, during periods when said amplifier circuit is gated "off", to retain the charge on said capacitor and thereby maintain dc balance throughout gated operation.
Claim 15
Dependent Claim
83 words
An amplifier circuit as in claim 11 in which said bias control means includes a first current path responsive to current flowing in the first transistor of said other stage for providing charge current to said capacitor, and a second current path responsive to current flowing in the second transistor of said other stage for providing discharge current to said capacitor, the voltage across said capacitor being substantially constant when said charge and discharge currents are equal for establishing said stable bias condition.
Claim 16
Dependent Claim
26 words
An amplifier circuit as in claim 13 in which said first and second current paths include semiconductor components providing reversed bias junctions during gated "off" periods.
Claim 17
Dependent Claim
82 words
An amplifier circuit as in claim 14 in which said first current path is arranged in a single current mirror configuration with the first transistor of said stage for providing current flow in a given direction with respect to said capacitor, and said second current path is arranged in a double current mirror configuration with the second transistor of each said other stage for providing current flow in a direction opposite to that of said given direction with respect to said capacitor.
Claim 18
Dependent Claim
32 words
An amplifier circuit as in claim 15 in which the differentially connected pair of transistors of said amplification stages are connected to current source transistors for controlling the transconductance of each stage.
Claim 19
Dependent Claim
65 words
An amplifier circuit as in claim 16 further comprising: (a) AGC control means for coupling an AGC signal to said current source transistors for controlling the transconductance of each stage as a function of said AGC signal, and (b) gate control means for applying a gate control signal for gating "on-off" said current source transistors and thereby controlling the gated operation of said amplifier circuit.
References Cited (Backward Citations)
US4172238A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-05 | 1985-04-06 | 1985-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-05 | 1989-04-06 | 1989-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-05 | 1993-04-06 | 1993-10-06 | $7700.00 | Window Closed / Lapsed |