US4292684A — Format for digital tape recorder

Claim 1

Independent Claim 329 words

A circuit for processing digital signals to be recorded on a single track of a suitable record medium, said circuit comprising means for encoding said digitized signal into a serialized signal suitable for recording on said record medium, said serialized signal containing a succession of frames in which each frame comprises a preselected number of data words, a preselected number of parity words, an error check code word corresponding to the frame and a sync word defining the frame location, said encoding means including means for generating the parity words of each frame by an exclusive -OR combination of data words of at least two other preselected frames according to the expression: P.sub.K.sup.N =D.sub.K+j.sup.(N-m).sup.⊕ D.sub.K+k.sup.(N+n) where P K N is a given parity word located at segment K of frame N, D K+j .sup.(N+n) is a given data word located at segment K+j of another preselected frame N+n located N frames ahead of frame N, where J is an integer, D K+k .sup.(N-m) is a given data word located at segment K+k of yet another preselected frame N-m, located m frames in back of frame N, where K is an integer, k is an integer, and m and n are integers not equal to 0, whereby each frame which is incorrectly played back may be detected, correct data words of that frame may be reconstructed from the data words of at least one of said other preselected frames N+n, located ahead of frame N in combination with the parity words P K generated from the data words of that frame and which are located behind frame N such that the placement of the parity words P K between the data words D N+n and D N-m ensures the availability of correctable data at every given position along the medium within the bounds of N-m to N+n and the corrected data words inserted into a serialized playback signal in place of the data words of the incorrectly played back frame.

Claim 2

Dependent Claim 329 words

A circuit for processing digital signals to be recorded on a single track of a suitable record medium, said circuit comprising means for encoding said digitized signal into a serialized signal suitable for recording on said record medium, said serialized signal containing a succession of frames in which each frame comprises a preselected number of data words, a preselected number of parity words, an error check code word corresponding to the frame and a sync word defining the frame location, said encoding means including means for generating the parity words of each frame by an exclusive -OR combination of data words of at least two other preselected frames according to the expression: P.sub.K.sup.N =D.sub.K+j.sup.(N-m).sup.⊕ D.sub.K+k.sup.(N+n) where P K N is a given parity word located at segment K of frame N, D K+j .sup.(N+n) is a given data word located at segment K+j of another preselected frame N+n located N frames ahead of frame N, where J is an integer, D K+k .sup.(N-m) is a given data word located at segment K+k of yet another preselected frame N-m, located m frames in back of frame N, where K is an integer, k is an integer, and m and n are integers not equal to 0, whereby each frame which is incorrectly played back may be detected, correct data words of that frame may be reconstructed from the data words of at least one of said other preselected frames N+n, located ahead of frame N in combination with the parity words P K generated from the data words of that frame and which are located behind frame N such that the placement of the parity words P K between the data words D N+n and D N-m ensures the availability of correctable data at every given position along the medium within the bounds of N-m to N+n and the corrected data words inserted into a serialized playback signal in place of the data words of the incorrectly played back frame.

Claim 3

Dependent Claim 98 words

A circuit according to claim 1, wherein said encoding means includes means for generating each parity word P K N from the exclusive OR combination of data words D 2K N+n and D 2K+k N-m such that n and m are sufficiently large integers that frames N+n and N-m are each spatially separated from frame N an interval of time to minimize the possibility that a single defect on a record medium onto which the encoded signals are recorded will cause a loss of signals upon playback from both frame N and either frame N+n or frame N-m.

Claim 4

Dependent Claim 32 words

A circuit according to claim 2 wherein m=n such that said parity word generating means generates the parity words of frame N from frames located n and -n frames from frame N.

Claim 5

Dependent Claim 54 words

A circuit according to claim 2, wherein said parity word generating means includes means for generating the parity words at each spatial segment K of said frame N from the data words at a predetermined segment 2K of frame N+15 and from the data words at a predetermined spatial segment 2K+1 of frame N-15.

Claim 6

Dependent Claim 48 words

A circuit according to claim 1, wherein said encoding means further comprises means for temporarily storing a given data word and assembling said word with another data word occurring later in time to form frames within which spatially adjacent data words correspond to data words displaced in time.

Claim 7

Dependent Claim 201 words

A circuit according to claim 1, further comprising a playback section including (a) means for providing a digital playback signal corresponding to recorded data on a said record medium, (b) means for processing said digital playback signal to determine the presence of erroneous signals within a frame including means for regenerating an error check code word corresponding to a received frame and means for comparing the regenerated error check word with a received error check code word of that frame to provide a frame error signal indicative of said erroneous signals in the absence of a match between the two, and (c) means responsive to a frame error signal for reconstructing a corrected data word and for inserting the corrected data words in place of the erroneous signals, including means for temporarily storing playback signals corresponding to each frame until signals corresponding to the preselected frames containing the parity and data words required for reconstruction of data words of said erroneous frame are received, means for reconstructing corrected data words from the received parity and data words within said preselected frames and means for inserting the reconstructed corrected data words in the proper spatial location within the processed digital playback signal.

Claim 8

Dependent Claim 135 words

A circuit according to claim 6, wherein the frame reconstruction means of the playback section includes memory means synchronized to the play control and time generator means and responsive to the data words and parity words of each frame and to the error frame signals from the processing means for cyclically storing said data words, said parity words, and said frame error signals, error frame correction circuit means comprising a pair of parity/data word latch means, and exclusive OR circuit means responsive to the status of the parity/data latch means and to regenerate corrected data words in response to an error frame signal, wherein the corrected data words are coupled through the exclusive OR means and are reinserted into the memory means in place of the previously stored data words of the detected erroneous frames.

Claim 9

Dependent Claim 42 words

A circuit according to claim 1, adapted for processing analog audio signals to be digitized and serially recorded, further comprising means for converting an input analog audio signal into a corresponding digitized audio signal for subsequent encoding as said input digitized signal.

Claim 10

Dependent Claim 41 words

A circuit according to claim 1, adapted for processing video signals to be digitized and serially recorded, further comprising means for converting an input analog video signal into a corresponding digitized video signal for subsequent encoding as said input digitized signal.

Claim 11

Dependent Claim 72 words

A circuit according to claim 1 adapted for processing high density digital data, wherein said encoding means includes means for formatting a given record of digital data into a train consisting of a plurality of frames, each frame containing a preselected number of data words, the beginning of each said record being identified by an initiate key signal and having an inter record gap signal associated with the end of the record.

Claim 12

Dependent Claim 24 words

A circuit according to claim 10 wherein said encoding means includes means for formatting frames wherein K=1 to 262, m=+2, n=-2, k=0, and j=0.

Claim 13

Dependent Claim 28 words

A circuit according to claim 1, wherein the playback section further includes means for converting the processed and corrected digital playback signal into a corresponding analog output signal.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1984-09-28	1985-03-30	1985-09-29	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1988-09-28	1989-03-30	1989-09-29	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1992-09-28	1993-03-30	1993-09-29	$7700.00	Window Closed / Lapsed

Format for digital tape recorder

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