Stv Subscriber address system

Claim 2

In a system wherein each of a plurality of television receivers is identified by a unique address code, a method for addressing selected ones of said plurality of television receivers comprising the steps of: transmitting during a first predetermined horizontal scanning line of the vertical interval of a broadcast television signal an address code portion which is common to the address codes identifying at least a group of said selected television receivers; transmitting during a second predetermined horizontal scanning line of the vertical interval of a broadcast television signal the remaining portions of the address codes identifying at least two of said selected television receivers of said group; and decoding said transmissions for addressing said at least two television receivers.

Claim 5

The method according to claim 2 including the step of transmitting an additional plurality of said different suffixes during a third predetermined horizontal scanning line of the vertical interval of a broadcast television signal.

Claim 6

The method according to claim 2 including the step of decoding said transmitted prefix and said transmitted suffixes at the site of each of said television receivers for identifying the television receivers associated with said group of address codes.

Claim 7

The method according to claim 4 wherein said decoding step comprises storing at the site of each of said television receivers the associated identifying address code and comparing at the site of each of said television receivers the stored address code with said transmitted prefix and said transmitted suffixes.

Claim 8

The method according to claim 4 including the step of operating a television receiver function of each of said identified television receivers.

Claim 11

A system according to claim 7 including means for transmitting during a third predetermined horizontal scanning line an additional plurality of suffix codes each comprising the n-p least significant bits of further different ones of said n-bit address codes of said group.

Claim 12

A system according to claim 8 wherein each of said decoding means comprises first comparison means operative for comparing said transmitted prefix code with the p most significant bits of the address code associated with the respective television receiver and second comparison means for comparing each of said transmitted suffix codes with the n-p least significant bits of the address code associated with the respective television receiver.

Claim 13

A system according to claim 9 wherein each of said television receivers includes a function operable in response to concurrent equality comparisons by said first and second comparison means.

Claim 14

A decoding circuit operable in association with a television receiver for determining coincidence between an n-bit receiver address code identifying said television receiver and an n-bit transmitted address code comprising a p-bit prefix code and an (n-p) bit suffix code, said prefix and suffix codes being transmitted respectively during different ones of the horizontal scanning lines of a broadcast television signal, said decoding circuit comprising: first means for storing said n-bit receiver address code; second means responsive to said transmitted television signal for storing the p-bit prefix code and the (n-p) bit suffix code transmitted during said different ones of said horizontal scanning lines; means responsive to said first and second means for comparing said stored p-bit prefix code with the p most significant bits of said stored receiver address code and for comparing said stored (n-p) bit suffix code with the (n-p) least significant bits of said stored receiver address code; and logic means for developing a signal indicating coincidence between said receiver address code and said transmitted address code in response to both of said comparisons indicating conditions of equality.

Claim 15

A decoding circuit operable in association with a television receiver for determining coincidence between an n-bit receiver address code identifying said television receiver and an n-bit transmitted address code comprising a p-bit prefix code and an (n-p) bit suffix code, said prefix and suffix codes being transmitted respectively during different ones of the horizontal scanning lines of a broadcast television signal, said decoding circuit comprising: first means for storing said n-bit receiver address code; second means responsive to said transmitted television signal for storing the p-bit prefix code and the (n-p) bit suffix code transmitted during said different ones of said horizontal scanning lines; means responsive to said first and second means for comparing said stored p-bit prefix code with the p most significant bits of said stored receiver address code and for comparing said stored (n-p) bit suffix code with the (n-p) least significant bits of said stored receiver address code; and logic means for developing a signal indicating coincidence between said receiver address code and said transmitted address code in response to both of said comparisons indicating conditions of equality.

Claim 16

The decoding circuit of claim 11 wherein a plurality of different (n-p) bit suffix codes are transmitted during one of said horizontal scanning lines, said means for comparing comprising means for comparing each of said different (n-p)-bit suffix codes with the (n-p) least significant bits of said stored receiver address code, said logic means developing said signal in response to said prefix comparison and any one of said suffix comparisons indicating conditions of equality.

Claim 17

The decoding circuit of claim 12 wherein said second means comprises means for temporarily storing in time succession the p-bit prefix code transmitted during a first of said horizontal scanning lines and the plurality of (n-p) bit suffix codes transmitted during a second of said horizontal scanning lines.

Claim 18

The decoding circuit of claim 13 wherein said second means comprises a multibit shift register having a data input connected for receiving the composite video signal from said television receiver and means for resetting said shift register at the beginning of each of said first and second horizontal scanning lines.

Claim 19

The decoding circuit of claim 13 wherein said means for comparing is operative for effecting said comparisons in a time successive manner in coordination with said second means.

Claim 20

The decoding circuit of claim 15 wherein said means for comparing comprises prefix comparator means operable for comparing said temporarily stored p-bit prefix code with the p most significant bits of said stored receiver address code and first latch means for developing an output signal in response to an equality condition therebetween.

Claim 21

The decoding circuit of claim 16 wherein said means for comparing further comprises suffix comparator means operable for comparing each of said plurality of temporarily stored (n-p) bit suffix codes with the (n-p) least significant bits of said stored receiver address code and second latch means for developing an output signal in response to an equality condition between any one of said plurality of comparisons.

Claim 22

The decoding circuit of claim 17 wherein said logic means comprises a coincidence gate responsive to said first and second latch means.

Claim 23

A decoding circuit operable in association with a television receiver for determining coincidence between an n-bit receiver address code identifying said television receiver and an n-bit transmitted address code comprising a p-bit prefix code and an (n-p) bit suffix code, said prefix code being transmitted during one of the horizontal scanning lines of a broadcast television signal and a plurality of different ones of said suffix codes being transmitted during a different one of the horizontal scanning lines of said broadcast television signal, said decoding circuit comprising: first means for storing said n-bit receiver address code; second means responsive to said transmitted television signal for storing said p-bit prefix code and said plurality of (n-p) bit suffix codes transmitted during said different ones of said horizontal scanning lines; means responsive to said first and second means for comparing said stored p-bit prefix code with the p most significant bits of said stored receiver address code and for comparing each of said plurality of stored (n-p) bit suffix codes with the (n-p) least significant bits of said stored receiver address code; and logic means for developing a signal indicating coincidence between said receiver address code and a transmitted address code in response to said prefix comparison and any one of said suffix comparisons indicating conditions of equality.

Claim 24

A decoding circuit operable in association with a television receiver for determining coincidence between an n-bit receiver address code identifying said television receiver and an n-bit transmitted address code comprising a p-bit prefix code and an (n-p) bit suffix code, said prefix code being transmitted during one of the horizontal scanning lines of a broadcast television signal and a plurality of different ones of said suffix codes being transmitted during a different one of the horizontal scanning lines of said broadcast television signal, said decoding circuit comprising: first means for storing said n-bit receiver address code; second means responsive to said transmitted television signal for storing said p-bit prefix code and said plurality of (n-p) bit suffix codes transmitted during said different ones of said horizontal scanning lines; means responsive to said first and second means for comparing said stored p-bit prefix code with the p most significant bits of said stored receiver address code and for comparing each of said plurality of stored (n-p) bit suffix codes with the (n-p) least significant bits of said stored receiver address code; and logic means for developing a signal indicating coincidence between said receiver address code and a transmitted address code in response to said prefix comparison and any one of said suffix comparisons indicating conditions of equality.

Claim 25

A decoding circuit operable in association with a television receiver for determining coincidence between an n-bit receiver address code identifying said television receiver and an n-bit transmitted address code comprising a p-bit prefix code and an (n-p) bit suffix code, said prefix code being transmitted during one of the horizontal scanning lines of a broadcast television signal and a plurality of different ones of said suffix codes being transmitted during a different one of the horizontal scanning lines of said broadcast television signal, said decoding circuit comprising: first means for storing said n-bit receiver address code; second means responsive to said transmitted television signal for temporarily storing in time succession the p-bit prefix code transmitted during said one horizontal scanning line and the plurality of (n-p) bit suffix codes transmitted during said different horizontal scanning line; prefix comparator means for comparing said temporarily stored p-bit prefix code with the p most significant bits of said stored receiver address code and including first latch means for developing an output signal in response to an equality condition therebetween; suffix comparator means for comparing each of said plurality of temporarily stored (n-p) bit suffix codes with the (n-p) least significant bits of said stored receiver address code and including second latch means for developing an output signal in response to an equality condition between any one of said plurality of comparisons; and logic means coupled to said first and second latch means for developing a signal indicating coincidence between said receiver address code and a transmitted address code in response to coincidence between said latch means output signals.

Claim 26

A decoding circuit operable in association with a television receiver for determining coincidence between an n-bit receiver address code identifying said television receiver and an n-bit transmitted address code comprising a p-bit prefix code and an (n-p) bit suffix code, said prefix code being transmitted during one of the horizontal scanning lines of a broadcast television signal and a plurality of different ones of said suffix codes being transmitted during a different one of the horizontal scanning lines of said broadcast television signal, said decoding circuit comprising: first means for storing said n-bit receiver address code; second means responsive to said transmitted television signal for temporarily storing in time succession the p-bit prefix code transmitted during said one horizontal scanning line and the plurality of (n-p) bit suffix codes transmitted during said different horizontal scanning line; prefix comparator means for comparing said temporarily stored p-bit prefix code with the p most significant bits of said stored receiver address code and including first latch means for developing an output signal in response to an equality condition therebetween; suffix comparator means for comparing each of said plurality of temporarily stored (n-p) bit suffix codes with the (n-p) least significant bits of said stored receiver address code and including second latch means for developing an output signal in response to an equality condition between any one of said plurality of comparisons; and logic means coupled to said first and second latch means for developing a signal indicating coincidence between said receiver address code and a transmitted address code in response to coincidence between said latch means output signals.