Semiconductor package and electronic array having improved heat dissipation

Claim 2

An electronic array comprising a substrate having a conductive lead pattern and a plurality of sets of contacts on a major surface, each set of contacts being configured to receive contacts of a semiconductor chip, a closed length of bond receptive material surrounding each set of contacts, a plurality of semiconductor chips, each of said chips having a plurality of contacts on one surface with said plurality of contacts attached to one of said sets of contacts on said major surface, a plurality of heat dissipation members each with a contact surface having an area greater than the area of a corresponding one of said chips and each having an outer wall formed at the termination of said contact surface, means attaching each chip to a central region of the contact surface of a heat dissipation member, and means bonded to the outer wall of each of said heat dissipation members and to one of said closed length of bond receptive material for enclosing each of said chips.

Claim 3

An electronic array as defined by claim 1 wherein said means attaching each chip comprises a heat conductive plate.

Claim 4

An electronic array as defined by claim 2 wherein said means for enclosing each of said chips comprises an annular ring.

Claim 5

An electronic array as defined by claim 3 wherein each of said annular rings is soldered to said heat dissipation members and to said closed length of bond receptive material.

Claim 6

An electronic array as defined by claim 4 wherein said closed length of bond receptive material comprises chrome-gold, each of said annular rings comprises copper, and said heat dissipation member comprises copper.

Claim 7

An electronic array as defined by claim 3 wherein each of said annular rings is adhesively bonded to said heat dissipation member and soldered to said closed length of bond receptive material.

Claim 8

An electronic array as defined by claim 2 wherein each of said plates comprises a ceramic with a layer of solderable material on each major surface of each of said plates.

Claim 9

An electronic array as defined by claim 7 wherein said ceramic comprises beryllia and said solderable material comprises nickel-gold.

Claim 10

An electronic array as defined by claim 1 wherein said plurality of contacts on each of said chips comprises beam leads.

Claim 11

An electronic array as defined by claim 1 wherein said substrate comprises a ceramic with said conductive lead pattern comprising a multiple layer of conductive material.

Claim 12

An electronic array as defined by claim 10 wherein said substrate further includes a plurality of electrical contacts whereby said substrate can be electrically interconnected with other circuitry.

Claim 13

A hermetically sealed semiconductor package comprising a substrate having a major surface, a plurality of contacts on said substrate, a semiconductor chip, a plurality of electrical contacts on said chip, means attaching said plurality of electrical contacts on said chip to said plurality of contacts on said substrate, heat dissipation means with a contact surface having an area greater than the area of a chip and with an outer wall surrounding said contact surface, means attaching said chip to a central region of said heat dissipation means, and sealing means attached to the outer wall of said heat dissipation means and to said substrate and hermetically sealing said semiconductor chip.

Claim 14

A hermetically sealed semiconductor package comprising a substrate having a major surface, a plurality of contacts on said substrate, a semiconductor chip, a plurality of electrical contacts on said chip, means attaching said plurality of electrical contacts on said chip to said plurality of contacts on said substrate, heat dissipation means with a contact surface having an area greater than the area of a chip and with an outer wall surrounding said contact surface, means attaching said chip to a central region of said heat dissipation means, and sealing means attached to the outer wall of said heat dissipation means and to said substrate and hermetically sealing said semiconductor chip.

Claim 15

A hermetically sealed semiconductor package as defined by claim 12 wherein said means attaching said heat dissipation means to said chip comprises a heat conductive plate.

Claim 16

A hermetically sealed semiconductor package as defined by claim 13 wherein said sealing means comprises an annular ring.

Claim 17

A hermetically sealed semiconductor package as defined by claim 14 wherein said annular ring is soldered to said heat dissipation means and to said substrate.

Claim 18

A hermetically sealed semiconductor package as defined by claim 13 wherein said means attaching said plate to said chip and to said heat dissipation comprises solder.

Claim 19

A hermetically sealed semiconductor package as defined by claim 16 wherein said means attaching said plurality of electrical contacts on said chip to said plurality of contacts on said substrate comprises thermo compression bonds.

Claim 20

A hermetically sealed semiconductor package as defined by claim 17 wherein said sealing means comprises an annular ring and wherein said annular ring is soldered to said heat dissipation means and to said substrate.

Claim 21

A hermetically sealed semiconductor package as defined by claim 12 wherein said substrate includes a conductive lead pattern electrically interconnecting said semiconductor chip to a plurality of other semiconductor chips on said substrate.

Claim 22

An electronic array comprising a substrate having a conductive lead pattern and a plurality of sets of contacts on a major surface, each set of contacts being configured to receive contacts of a semiconductor chip, a closed length of bond receptive material surrounding each set of contacts, a plurality of semiconductor chips, each of said chips having a plurality of contacts on a first surface with said plurality of contacts attached to one of said sets of contacts on said major surface, each of said chips having a second surface substantially parallel to said first surface for transfer of heat from said chips, each of said chips having a thickness measured between said first and second surfaces, a plurality of heat dissipation members each with a contact surface having an area greater than the area of a corresponding second surface of said chips and each having an outer wall terminating said contact surface, said outer wall extending at an angle to said contact surface, means attaching said second surface of each chip to a central region of the contact surface of a corresponding heat dissipation member whereby a gap is provided between an outer region of the contact surface and said major surface where the gap dimension includes the thickness of the chip, and means bonded to the outer wall of each of said heat dissipation members and to one of said closed length of bond receptive material for enclosing said gap and each of said chips irrespective of the dimensions of the gaps and the thickness of said chips.

Claim 23

An electronic array comprising a substrate having a conductive lead pattern and a plurality of sets of contacts on a major surface, each set of contacts being configured to receive contacts of a semiconductor chip, a closed length of bond receptive material surrounding each set of contacts, a plurality of semiconductor chips, each of said chips having a plurality of contacts on a first surface with said plurality of contacts attached to one of said sets of contacts on said major surface, each of said chips having a second surface substantially parallel to said first surface for transfer of heat from said chips, each of said chips having a thickness measured between said first and second surfaces, a plurality of heat dissipation members each with a contact surface having an area greater than the area of a corresponding second surface of said chips and each having an outer wall terminating said contact surface, said outer wall extending at an angle to said contact surface, means attaching said second surface of each chip to a central region of the contact surface of a corresponding heat dissipation member whereby a gap is provided between an outer region of the contact surface and said major surface where the gap dimension includes the thickness of the chip, and means bonded to the outer wall of each of said heat dissipation members and to one of said closed length of bond receptive material for enclosing said gap and each of said chips irrespective of the dimensions of the gaps and the thickness of said chips.