Abstract This invention uses a plurality of bubble memory chips in a system for providing simultaneous input and output in a word or byte organized output. Each bubble memory chip has the same number of minor loops as is required for nominal memory size without the requirement for extra or redundant loops. Each bubble memory chip may have a number of faulty minor loops where the bit output is incorrect and cannot be used. However, a requirement for this system is that no two bubble memory chips may have a faulty bit or minor loop at the same major loop address location. An additional bubble memory chip is provided which will contain the correct data bits for locations corresponding to defective major loop addresses in the bubble memory chips making up the byte. A Programmable Read Only Memory (PROM) is provided and connected with a logic network to control the gating of the outputs of the bubble memory chips associated with the memory byte and the extra bubble memory chip to control the gating of the outputs. Thus, as contents of the various bubble memory chips are addressed, the PROM controls the gating of the bits forming the output byte or word so that the output byte or word is comprised of only correct bits.
A word organized, fault tolerant bubble memory system comprising: a plurality of bubble memory chips, each having the same number of minor loops as is required for a nominal memory size, equivalent in number to the word size of the memory system, a correction bit bubble memory chip, memory means responsive to input addresses for identifying defective bit locations in said plurality of bubble memory chips, means for providing addresses to said memory means and to said memory system, means for substituting, in reading and writing operations, correction bits from said correction bit bubble memory chip for bits in any one of said plurality of bubble memory chips in response to output signals from said memory means identifying a defective bit location, wherein said means for substituting is comprised of a decoder associated with an output address from said memory means for identifying a particular one of said plurality of bubble memory chips having a defective location and logic gate means which in response to a signal from said decoder connects said correction bit chip with the appropriate input or output of said memory system in reading and writing operations, said logic gate means being comprised of AND gates associated with each of said bubble memory chips, each of said AND gates receiving a common data bit input from said correction bit bubble memory chip and a unique input from said decoder for gating said input in response to an enable signal from said decoder together with AND gate means for disabling the output from any one of said bubble memory chips in response to an inverted enable signal from said decoder when a bit from said correction bit chip is to be gated.
Claim 2
Dependent Claim
284 words
A word organized, fault tolerant bubble memory system comprising: a plurality of bubble memory chips, each having the same number of minor loops as is required for a nominal memory size, equivalent in number to the word size of the memory system, a correction bit bubble memory chip, memory means responsive to input addresses for identifying defective bit locations in said plurality of bubble memory chips, means for providing addresses to said memory means and to said memory system, means for substituting, in reading and writing operations, correction bits from said correction bit bubble memory chip for bits in any one of said plurality of bubble memory chips in response to output signals from said memory means identifying a defective bit location, wherein said means for substituting is comprised of a decoder associated with an output address from said memory means for identifying a particular one of said plurality of bubble memory chips having a defective location and logic gate means which in response to a signal from said decoder connects said correction bit chip with the appropriate input or output of said memory system in reading and writing operations, said logic gate means being comprised of AND gates associated with each of said bubble memory chips, each of said AND gates receiving a common data bit input from said correction bit bubble memory chip and a unique input from said decoder for gating said input in response to an enable signal from said decoder together with AND gate means for disabling the output from any one of said bubble memory chips in response to an inverted enable signal from said decoder when a bit from said correction bit chip is to be gated.
Claim 3
Dependent Claim
21 words
The apparatus of claim 1 and further comprising means for disabling said decoder when no correction bit is to be gated.