Programmable controller with data archive

Claim 2

An improved digital controller of the type having a random-access read/write memory which stores control data that is used in controlling a machine, wherein the improvement comprises: an erasable, read-mostly memory, for nonvolatile storage of control data; loading means coupled to both the read/write memory and the read-mostly memory for transferring control data from the read/write memory into the read-mostly memory to form a non-volatile master copy; data-checking means coupled to the read/write memory for verifying the control data in the read/write memory; and reloading means, coupled to both the read/write memory and the read-mostly memory and responsive to a failure of the data-checking means to verify the control data in the read/write memory, for transferring the master copy of control data from the read-mostly memory into the read/write memory.

Claim 3

The improved controller of claim 1, wherein the data-checking means is operable to verify the control data in the read/write memory before this data is used in controlling the machine.

Claim 4

The improved controller of claim 1, further comprising: watchdog timer means for generating fault signals in response to faults that occur during operation of the controller; wherein the data-checking means is responsive to a watchdog fault signal for testing the control data in the read/write memory; and wherein the reloading means is operable to transfer a master copy of control data from the read-mostly memory into the read/write memory if the control data in the read/write memory is not verified by the data-checking means.

Claim 5

The improved controller of claim 1, further comprising: mode selection means having a LOAD position and an alternate position; and wherein the loading means is responsive to sense the position of the load selection means, the loading means being operable, only when the mode selection means is in its LOAD position, to erase a previously stored master copy of control data in the read-mostly memory and to write updated control data into the read-mostly memory to form a new master copy of control data.

Claim 6

The improved controller of claim 1, further comprising: a user-operable LOAD control; and wherein the loading means is responsive to sense the status of the user-operable LOAD control prior to the transfer of control data from the read/write memory to the read-mostly memory, so that such transfer is conditioned upon the operation of the LOAD control by the user.

Claim 7

The improved controller of claim 1, wherein the control data transferred between the read/write memory and the read-mostly memory includes a block of control program instructions for controlling a machine.

Claim 8

A digital controller for controlling I/O devices on a machine through execution of control program instructions, the controller comprising: a read/write program memory which stores status data representing the status of the I/O devices on the machine and which stores control program instructions; a read-only memory which stores a plurality of processor instructions; an erasable, read-mostly archive memory for nonvolatile storage of the control program instructions; and controller processor means coupled to the read/write program memory, coupled to the read-only memory and coupled to the read-mostly archive memory, wherein the controller processor means reads the control program instructions from the read/write program memory and executes the control program instructions to operate on the status data, wherein the controller processor means is responsive to selected processor instructions in the read-only memory to copy program instructions from the read/write program memory into nonvolatile storage in the read-mostly archive memory, wherein the controller processor means is further responsive to other selected processor instructions in the read-only memory to verify the integrity of the control program instructions stored in the read/write program memory, and wherein the controller processor means is further responsive to other selected processor instructions in the read-only memory to reload the copied program instructions from the read-mostly archive memory into the read/write program memory in response to a failure to verify the integrity of the control program instructions stored in the read/write program memory.

Claim 9

A digital controller for controlling I/O devices on a machine through execution of control program instructions, the controller comprising: a read/write program memory which stores status data representing the status of the I/O devices on the machine and which stores control program instructions; a read-only memory which stores a plurality of processor instructions; an erasable, read-mostly archive memory for nonvolatile storage of the control program instructions; and controller processor means coupled to the read/write program memory, coupled to the read-only memory and coupled to the read-mostly archive memory, wherein the controller processor means reads the control program instructions from the read/write program memory and executes the control program instructions to operate on the status data, wherein the controller processor means is responsive to selected processor instructions in the read-only memory to copy program instructions from the read/write program memory into nonvolatile storage in the read-mostly archive memory, wherein the controller processor means is further responsive to other selected processor instructions in the read-only memory to verify the integrity of the control program instructions stored in the read/write program memory, and wherein the controller processor means is further responsive to other selected processor instructions in the read-only memory to reload the copied program instructions from the read-mostly archive memory into the read/write program memory in response to a failure to verify the integrity of the control program instructions stored in the read/write program memory.

Claim 10

The digital controller of claim 7, further comprising: mode selection means having a LOAD position and an alternate position; further comprising means for coupling the mode selection means to the processor means; wherein the controller processor means includes enabling circuit means for controlling write and erase functions on the read-mostly memory; and wherein the controller processor means is further responsive to selected processor instructions to read the status of the mode selection means, and is further responsive to other selected processor instructions to signal the enabling circuit means to disable the write and erase functions on the read-mostly memory when the mode selection means is in its alternate position to prevent spurious overwriting of any of the contents of the read-mostly memory.

Claim 11

The digital controller of claim 7, further comprising: a user-operable LOAD control; further comprising means for coupling the LOAD control to the processor means; and wherein the controller processor means is further responsive to other selected processor instructions to sense the status of the LOAD control prior to the transfer of control program instructions from the read/write memory to the read-mostly memory, so that such transfer is conditioned upon the operation of the LOAD control by the user.

Claim 12

The digital controller of claim 7, further comprising: fault detection circuit means coupled to both processor means and the read/write memory, the fault detection circuit means being responsive to the detection of faults to generate nonmaskable interrupt signals to the processor means, the fault detection circuit means also being responsive to a signal to inhibit the generation of such nonmaskable interrupt signals; and wherein the processor means is responsive to a selected processor instruction in the read-only memory to generate the signal to the fault detection means to inhibit the generation of such nonmaskable interrupt signals during the response of the processor means to processor instructions for reloading the copied control program instructions from the read-mostly memory into the random-access memory.

Claim 13

The digital controller of claim 7, wherein the read-mostly memory is an electronic memory.

Claim 14

In a digital controller for controlling a machine through input and output devices thereon, a programmable module which is electrically coupled to the input and output devices and which executes control program instructions to operate on data representing the status of the output devices in response to data representing the status of the input devices, the programmable module comprising: a read/write program memory which stores input status data representing the status of the input devices and output status data representing the status of the output devices and which stores control program instructions; a read-only memory which stores a plurality of processor instructions; an erasable, read-mostly archive memory for nonvolatile storage of control program instructions; an address bus and a data bus; controller processor means coupled through both the address bus and the data bus to each of said memories, and program panel interface means coupled to both the controller processor means and to the read/write program memory through the data bus and further coupled to the controller processor through an interrupt control line, wherein the controller processor means reads the control program instructions from the read/write program memory and executes the control program instructions to examine input status data and determine output status data, wherein the controller processor means is responsive to selected processor instructions in the read-only memory to sequentially couple addresses through the address bus to the read/write program memory and to the read-mostly archive memory to copy program instructions from the read/write program memory into nonvolatile storage in the read-mostly archive memory through the data bus, wherein the controller processor means is further responsive to other selected processor instructions in the read-only memory to sequentially couple addresses through the address bus to the read/write program memory and to the read-mostly archive memory to reload the copied program instructions from the read-mostly archive memory into the read/write program memory through the data bus, and wherein the controller processor means is further responsive to an interrupt signal generated by the program panel interface means to couple original and edited program instructions through the data bus between the program panel interface means and the read/write program memory, prior to copying such instructions into the read-mostly archive memory.

Claim 15

In a digital controller for controlling a machine through input and output devices thereon, a programmable module which is electrically coupled to the input and output devices and which executes control program instructions to operate on data representing the status of the output devices in response to data representing the status of the input devices, the programmable module comprising: a read/write program memory which stores input status data representing the status of the input devices and output status data representing the status of the output devices and which stores control program instructions; a read-only memory which stores a plurality of processor instructions; an erasable, read-mostly archive memory for nonvolatile storage of control program instructions; an address bus and a data bus; controller processor means coupled through both the address bus and the data bus to each of said memories, and program panel interface means coupled to both the controller processor means and to the read/write program memory through the data bus and further coupled to the controller processor through an interrupt control line, wherein the controller processor means reads the control program instructions from the read/write program memory and executes the control program instructions to examine input status data and determine output status data, wherein the controller processor means is responsive to selected processor instructions in the read-only memory to sequentially couple addresses through the address bus to the read/write program memory and to the read-mostly archive memory to copy program instructions from the read/write program memory into nonvolatile storage in the read-mostly archive memory through the data bus, wherein the controller processor means is further responsive to other selected processor instructions in the read-only memory to sequentially couple addresses through the address bus to the read/write program memory and to the read-mostly archive memory to reload the copied program instructions from the read-mostly archive memory into the read/write program memory through the data bus, and wherein the controller processor means is further responsive to an interrupt signal generated by the program panel interface means to couple original and edited program instructions through the data bus between the program panel interface means and the read/write program memory, prior to copying such instructions into the read-mostly archive memory.