Memory and control circuit for the memory

Claim 2

A memory and control circuit for the memory comprising: a memory including a first memory plane area having a plurality of semiconductor memory cell elements and a second memory plane area superimposed on said first memory plane area and having a plurality of non-volatile memory cell elements formed of insulated gate field effect semiconductor devices each having a gate electrode, said first and second memory plane areas being each divided into a plurality of blocks and the memory cell elements of the first memory plane area being respectively connected to the corresponding memory cell elements of the second memory plane area in one-to-one correspondence to permit data transfer between the memory cell element of the first memory plane area and the corresponding memory cell element of the second memory plane area; address designating means connected to the first memory plane area to designate an address of the memory cell element of the first memory plane area; a control signal generator for generating a read/write control signal to cause the first memory plane area to be set to a write or readout mode; and control means connected to the gate electrodes of said non-volatile memory cell elements for initiating data transfer between that memory cell element in the first memory plane area which is addressed by said address designating means and the corresponding memory cell element in the second memory plane area, said blocks being controlled independently from each other.

Claim 3

A memory and control circuit for the memory according to claim 1, further including block designating means for selectively designating the blocks in the second memory plane area.

Claim 4

A memory and control circuit for the memory according to claim 2, further including block signal generating means for generating a block signal representing a block to be designated and said block designating means designates a selected block according to the block signal of the block signal generating means.

Claim 5

A memory and control circuit for the memory according to claim 3, in which there are further included block signal generating means for generating a block signal representing a block to be designated, means for selectively designating the blocks of the second memory plane area according to the block signal of said block signal generating means, and a register storing a block signal from said block signal generating means and selectively generating, in response to an output signal from said control means, write prohibiting signal to that block of the first memory plane area which corresponds to the block signal stored.

Claim 6

A memory and control circuit for the memory according to claim 1, wherein said plurality of memory cell elements of said first memory plane area are formed to constitute a random access memory.

Claim 7

A memory and control circuit for the memory according to claim 1, further including block designating means for selectively designating the blocks in the second memory plane area.

Claim 8

A memory and control circuit for the memory according to claim 6, further including block signal generating means for generating a block signal representing a block to be designated and said block designating means designates a selected block according to the block signal of the block signal generating means.

Claim 9

A memory and control circuit for the memory according to claim 1 in which said first and second memory plane areas are each divided into a plurality of blocks and data transfer between the first and second memory plane areas is effected for each block, and in which there are further included block signal generating means for generating a block signal representing a block to be designated, means for selectively designating the blocks of the second memory plane area according to the block signal of said block signal generating means, and a register storing a block signal from said block signal generating means and selectively generating, in response to an output signal from said control means, write operation inhibiting signal.

Claim 10

A memory and control circuit for the memory comprising: a memory including a first memory plane area having a plurality of semiconductor memory cell elements and a plurality of second memory plane areas superimposed one over the other on said first memory plane area and each having a plurality of non-volatile memory cell elements formed of insulated gate field effect semiconductor devices each having a gate electrode, said first and second memory plane areas being each divided into a plurality of blocks and the memory cell elements of the first memory plane area being respectively connected to the corresponding memory cell elements of each of the second memory plane areas to permit data transfer between the memory cell element of the first memory plane area and the corresponding memory cell element each of the second memory plane areas; address designating means connected to the first memory plane area to designate an address of the memory cell element of the first memory plane area; a control signal generator for generating a read/write control signal to cause the first memory plane area to be set to a readout or write mode; and control means connected to the gate electrodes of said non-volatile memory cell elements for initiating data transfer between that memory cell element of the first memory plane area which is designated by said address designating means and the corresponding memory cell element in each of the second memory plane areas, said blocks being controlled independently from each other.

Claim 11

A memory and control circuit for the memory comprising: a memory including a first memory plane area having a plurality of semiconductor memory cell elements and a plurality of second memory plane areas superimposed one over the other on said first memory plane area and each having a plurality of non-volatile memory cell elements formed of insulated gate field effect semiconductor devices each having a gate electrode, said first and second memory plane areas being each divided into a plurality of blocks and the memory cell elements of the first memory plane area being respectively connected to the corresponding memory cell elements of each of the second memory plane areas to permit data transfer between the memory cell element of the first memory plane area and the corresponding memory cell element each of the second memory plane areas; address designating means connected to the first memory plane area to designate an address of the memory cell element of the first memory plane area; a control signal generator for generating a read/write control signal to cause the first memory plane area to be set to a readout or write mode; and control means connected to the gate electrodes of said non-volatile memory cell elements for initiating data transfer between that memory cell element of the first memory plane area which is designated by said address designating means and the corresponding memory cell element in each of the second memory plane areas, said blocks being controlled independently from each other.

Claim 12

A memory and control circuit for the memory according to claim 9, wherein said plurality of memory cell elements of said first memory plane area are formed to constitute a random access memory.

Claim 13

A memory and control circuit for the memory according to claim 9, further including block designating means for selectively designating the blocks in the second memory plane area.

Claim 14

A memory and control circuit for the memory according to claim 11, further including block signal generating means for generating a block signal representing a block to be designated and said block designating means designates a selected block according to the block signal of the block signal generating means.

Claim 15

A memory and control circuit for the memory according to claim 9 in which said first and second memory plane areas are each divided into a plurality of blocks and data transfer between the first and second memory plane areas is effected for each block, and in which there are further included block signal generating means for generating a block signal representing a block to be designated, means for selectively designating the blocks of the second memory plane area according to the block signal of said block signal generating means, and a register storing a block signal from said block signal generating means and selectively generating in response to an output signal from said control means, write prohibiting signals to that block of the first memory plane area which corresponds to the block signal stored.