Patent US4291325A successfully refreshed from Google Patents.
US4291325A
Expired / Lapsed
US
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Dual gate controlled thyristor with highly doped cathode base grid covered with high resistivity base layer
Assignee: Meidensha Corp
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Filing: 1980-01-04
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Granted: 1981-09-22
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Expires: 2000-01-04
Abstract
Abstract A gate controlled semiconductor device comprises two main electrode members provided on a wafer having at least one junction formed between two alternately different conductivity typed semiconductive layers and a control electrode member in which the same or a different conductivity typed surface is provided on one layer of the wafer. The control electrode member is provided on the wafer adjacent one of the main electrodes. The control electrode member includes a low resistance layer embedded in one surface of the wafer and consists of a wide bridging portion, a plurality of relatively wide main trunk portions projecting from the bridging portion and a plurality of narrow branch portions branching from the main trunk portions.
Inventors
- 👤 Tetsuro Sueoka
- 👤 Satoshi Ishibashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:13
CPC Classifications
H; H10; H10D; H10D18/00; H10D18/60; H10D64/00; H10D64/20; H10D64/27; H10D64/291
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
259 words
A gate controlled semiconductor device comprising: a semiconductor wafer made of: a first layer of one conductivity type; a second layer of an opposite conductivity type, connected to the first layer; a third layer of said one conductivity type connected to said second layer; said first and third layers having exposed surfaces; a high resistance layer of said one conductivity type formed on said third layer at said surface thereof to a selected depth; and a fourth layer of said second conductivity type connected into said high resistance layer having a surface; an anode electrode connected to said first layer exposed surface; a cathode electrode connected to said fourth layer surface; a first gate electrode layer connected to an exposed surface of said high resistance layer; said third layer having a first slot in the exposed surface thereof; a first low resistance layer at the bottom of said first slot; said third layer having a plurality of second slots extending into said fourth layer and communicating with said first slot; a second low resistance layer at the bottom of each of said plurality of second slots connected to said first low resistance layer; a second gate electrode layer for supplying an OFF signal to the device connected over a surface of said first and second low resistance layers; and at least one buried low resistance layer which is narrower than said first and second low resistance layers; embedded in said third layer and spaced from said second and fourth layers, connected to each of said second low resistance layers.
Claim 2
Dependent Claim
259 words
A gate controlled semiconductor device comprising: a semiconductor wafer made of: a first layer of one conductivity type; a second layer of an opposite conductivity type, connected to the first layer; a third layer of said one conductivity type connected to said second layer; said first and third layers having exposed surfaces; a high resistance layer of said one conductivity type formed on said third layer at said surface thereof to a selected depth; and a fourth layer of said second conductivity type connected into said high resistance layer having a surface; an anode electrode connected to said first layer exposed surface; a cathode electrode connected to said fourth layer surface; a first gate electrode layer connected to an exposed surface of said high resistance layer; said third layer having a first slot in the exposed surface thereof; a first low resistance layer at the bottom of said first slot; said third layer having a plurality of second slots extending into said fourth layer and communicating with said first slot; a second low resistance layer at the bottom of each of said plurality of second slots connected to said first low resistance layer; a second gate electrode layer for supplying an OFF signal to the device connected over a surface of said first and second low resistance layers; and at least one buried low resistance layer which is narrower than said first and second low resistance layers; embedded in said third layer and spaced from said second and fourth layers, connected to each of said second low resistance layers.
Claim 3
Dependent Claim
19 words
A device according to claim 1, wherein said first and second low resistance layers comprise high density impurity layers.
Claim 4
Dependent Claim
19 words
A device according to claim 2, wherein said high density impurity layers are formed of said one conductivity type.
Claim 5
Dependent Claim
174 words
A device according to claim 1, wherein said wafer is disc-shaped, said first layer comprising a P-type P 1 layer, said second layer comprising a N-type N 1 , layer, said third layer comprising a P-type P 2 layer, said high resistance layer comprising a P-type P 2 - layer formed in said P 2 layer, said fourth layer comprising an N-type N 2 layer formed in a disc-shape and having a hole in the center thereof through which a portion of said P 2 layer extends, said anode electrode comprising a metal layer adhered to an exposed surface of said P 1 layer, said cathode electrode comprising a metal layer adhered to an exposed surface of said N 2 layer, said first gate electrode layer comprising a metal layer adhered to an exposed surface of said high resistance P 2 - layer and said second gate electrode layer comprising a metal layer adhered to said first and second low resistance layers, said first and second low resistance layers, comprising high density impurity layers.
Claim 6
Dependent Claim
101 words
A device according to claim 4, wherein said first slot comprises a ring-shaped slot formed adjacent an outer edge of said disc-shaped wafer, said first low resistance layer being ring-shaped and provided in said first slot, said plurality of second slots extending radially inwardly of said first slot, said second low resistance layers extending radially inwardly of said first low resistance layer, and additional buried low resistance layers, each of said additional and at least one buried low resistance layer comprising concentric ring-shaped layers disposed radially inwardly of said first slot each connected to said radially extending second low resistance layers.
Claim 7
Dependent Claim
36 words
A device according to claim 4, wherein said cathode electrode comprises a disc-shaped metal layer adhered to said N 2 layer and a disc-shaped metal plate contacting an exposed surface of said cathode electrode metal layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-21 | 1985-03-23 | 1985-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-21 | 1989-03-23 | 1989-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-21 | 1993-03-23 | 1993-09-22 | $7700.00 | Window Closed / Lapsed |