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US4290188A Expired / Lapsed US ⏱️ 0.0 years remaining

Process for producing bipolar semiconductor device utilizing predeposition of dopant and a polycrystalline silicon-gold film followed by simultaneous diffusion

Assignee: Fujitsu Ltd
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Filing: 1980-01-30
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Granted: 1981-09-22
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Expires: 2000-01-30
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Abstract

Abstract A process for manufacturing a bipolar semiconductor device. An epitaxial layer is formed on a silicon wafer, and a base layer is formed by the diffusion of impurities having one conductivity type in a part of the epitaxial layer. Impurities having the opposite conductivity type are deposited in a part of the base layer, polycrystalline silicon is deposited on the entire surface of the wafer which is provided with windows for emitter, base and collector electrodes, and a gold-containing film is applied on the entire surface of the polycrystalline silicon layer. Impurities having the opposite conductivity type are deposited and driven into the base layer so as to form an emitter layer and simultaneously gold atoms are driven in through the collector windows into a collector layer of the epitaxial layer and through the base and emitter windows into the collector layer.

Inventors

  • 👤 Yoshito Ichinose
  • 👤 Takeshi Fukuda
  • 👤 Naoaki Kobayashi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 14:21
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/10; H10P32/18; H10D; H10D62/00; H10D62/80; H10D62/83; H10D62/834; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S148/00; Y10S148/062; Y10S148/122; Y10S438/00; Y10S438/904

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 162 words
A process for manufacturing a bipolar semiconductor device comprising the steps of: forming an epitaxial layer on a silicon wafer, said epitaxial layer comprising a collector layer of said device; forming a base layer of said device by diffusion of impurities having one conductivity type in a portion of said epitaxial layer within said collector layer; depositing an inpurity of the opposite conductivity type on a part of said base layer; selectively depositing polycrystalline silicon on the entire surface of said wafer to provide windows for emitter, base and collector electrodes of said device, applying a gold-containing film on the entire surface of the polycrystalline silicon layer; simultaneously driving (1) said deposited impurity having the opposite conductivity type into said part of said base layer so as to form an emitter layer within said base layer and (2) the atoms of said gold through said windows into the collector layer; and electrically connecting said emitter, base and collector layers within said device.
Claim 2
Dependent Claim 162 words
A process for manufacturing a bipolar semiconductor device comprising the steps of: forming an epitaxial layer on a silicon wafer, said epitaxial layer comprising a collector layer of said device; forming a base layer of said device by diffusion of impurities having one conductivity type in a portion of said epitaxial layer within said collector layer; depositing an inpurity of the opposite conductivity type on a part of said base layer; selectively depositing polycrystalline silicon on the entire surface of said wafer to provide windows for emitter, base and collector electrodes of said device, applying a gold-containing film on the entire surface of the polycrystalline silicon layer; simultaneously driving (1) said deposited impurity having the opposite conductivity type into said part of said base layer so as to form an emitter layer within said base layer and (2) the atoms of said gold through said windows into the collector layer; and electrically connecting said emitter, base and collector layers within said device.
Claim 3
Dependent Claim 56 words
A process as claimed in claim 1, wherein said electrically connecting step comprises the steps of: removing entirely said gold-containing film; depositing aluminum on said polycrystalline silicon layer; and patterning said aluminum and polycrystalline silicon and heating said wafer to form electrodes of double layers, one layer of aluminum and the other layer of aluminum silicide.
Claim 4
Dependent Claim 19 words
A process as claimed in claim 1, wherein said polycrystalline silicon is deposited by chemical vapor deposition utilizing silane.
Claim 5
Dependent Claim 41 words
A process as claimed in claim 1, wherein said gold-containing film is applied by spin coating an alcohol solution containing gold trichloride and silicic acid and drying said solution so as to form a thin film of silicon oxide containing gold.
Claim 6
Dependent Claim 42 words
A process as claimed in claim 1, said impurity comprising phosphorus, said process including depositing the phosphorus impurity from a gas containing phosphorus oxychloride and forming a phosphorus silicate glass as a passivation film on the surface of said silicon oxide layer.
Claim 7
Dependent Claim 45 words
A process as claimed in claim 1, 4, or 5, wherein the simultaneous driving in of said impurities having the opposite conductivity type and gold atoms is carried out by heating said silicon wafer at a temperature in the range from 900° to 1,200° C.
Claim 8
Dependent Claim 42 words
A process as claimed in claim 6, wherein the simultaneous driving in of said impurities having the opposite conductivity type and gold atoms is carried out by heating said silicon wafer at a temperature in the range from 1,050° to 1,100° C.
Claim 9
Dependent Claim 15 words
The process of claim 1 or 5, said bipolar device being of an n-p-n type.
Claim 10
Dependent Claim 16 words
The process of claim 1, 2, 3, 4, 5, or 7 comprising rapidly cooling said wafer.
Claim 11
Dependent Claim 21 words
The process of claim 4 comprising forming said film of gold-containing silicon oxide to have a thickness of about 1000 angstroms.

References Cited (Backward Citations)

US3473976A Cited
US3645808A Cited
US3775196A Cited
US3617398A Cited
US3946425A Cited
US3625781A Cited
US4146413A Cited
US4144106A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1984-09-21 1985-03-23 1985-09-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1988-09-21 1989-03-23 1989-09-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1992-09-21 1993-03-23 1993-09-22 $7700.00 Window Closed / Lapsed

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