Patent US3438787A successfully refreshed from Google Patents.
Patent US4290186A successfully refreshed from Google Patents.
US4290186A
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Method of making integrated semiconductor structure having an MOS and a capacitor device
Assignee: National Semiconductor Corp
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Filing: 1979-07-23
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Granted: 1981-09-22
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Expires: 1999-07-23
Abstract
Abstract This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity. Thus, the boron implanted region performs the important function of preventing a surface N type inversion layer from being formed across the semiconductor surface beneath the silicon dioxide insulating layer which could occur across the substrate P- surface if the arsenic implant region was made into the P- substrate without the P type boron implant. The arsenic implant is of N type conductivity and has a higher concentration of impurities than the boron implant region. The dielectric portion of the semiconductor capacitor is the portion of the silicon dioxide layer located on the surface of the arsenic implanted region. A doped polysilicon electrode is formed over this portion of the silicon dioxide insulating layer and provides the other plate of the capacitor structure. In another embodiment that is disclosed, this above described semiconductor capacitor structure or device is combined with an MOS device in a single integrated semiconductor structure in order to provide a single MOS memory cell for dynamic random access memory chip utilizing the MOS device and the capacitor. Preferably, the semiconductor capacitor is shown as a connected extension of either the source or drain region of the MOS device.
Inventors
- 👤 Thomas Klein
- 👤 Andrew G. Varadi
- 👤 Charles E. Boettcher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:00
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/30; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
324 words
A method for making an integrated semiconductor structure having an MOS semiconductor device and a semiconductor capacitor device comprising the steps of: forming a semiconductor region of one conductivity type within a higher resistivity semiconductor substrate region of the same type conductivity, forming a shallow semiconductor region of opposite conductivity type within said semiconductor region of one conductivity type located within said higher resistivity semiconductor substrate region of the same one type conductivity, forming an insulating layer on a surface of said semiconductor region of one conductivity type, said higher resistivity semiconductor substrate region of the same one type conductivity, and said shallow semiconductor region of opposite conductivity type, forming spaced polysilicon layer portions on the surface of said insulating layer over said shallow semiconductor region of opposite conductivity type and over a portion of said higher resistivity semiconductor substrate region of said one conductivity type spaced from said shallow semiconductor region of opposite conductivity type to be used as a self-aligned polysilicon gate electrode for the MOS semiconductor device, forming openings in said insulating layer on opposite sides of said polysilicon gate electrode layer portion for subsequently forming source and drain regions, forming source and drain regions for the MOS semiconductor device on opposite sides of said polysilicon gate electrode layer portion using said polysilicon gate electrode layer portion as a self-aligned mask which is doped during the step of forming said source and drain regions along with said polysilicon layer portion located over said shallow semiconductor region of opposite conductivity type to render both said polysilicon layer portions electrically conductive, said electrically conductive polysilicon layer portion located over said shallow semiconductor region of opposite conductivity type being one plate of the semiconductor capacitor device, the portion of said insulating layer located over said region of opposite conductivity type being the dielectric of said semiconductor capacitor device, and said region of opposite conductivity type being the other plate of said semiconductor capacitor device.
Claim 2
Independent Claim
324 words
A method for making an integrated semiconductor structure having an MOS semiconductor device and a semiconductor capacitor device comprising the steps of: forming a semiconductor region of one conductivity type within a higher resistivity semiconductor substrate region of the same type conductivity, forming a shallow semiconductor region of opposite conductivity type within said semiconductor region of one conductivity type located within said higher resistivity semiconductor substrate region of the same one type conductivity, forming an insulating layer on a surface of said semiconductor region of one conductivity type, said higher resistivity semiconductor substrate region of the same one type conductivity, and said shallow semiconductor region of opposite conductivity type, forming spaced polysilicon layer portions on the surface of said insulating layer over said shallow semiconductor region of opposite conductivity type and over a portion of said higher resistivity semiconductor substrate region of said one conductivity type spaced from said shallow semiconductor region of opposite conductivity type to be used as a self-aligned polysilicon gate electrode for the MOS semiconductor device, forming openings in said insulating layer on opposite sides of said polysilicon gate electrode layer portion for subsequently forming source and drain regions, forming source and drain regions for the MOS semiconductor device on opposite sides of said polysilicon gate electrode layer portion using said polysilicon gate electrode layer portion as a self-aligned mask which is doped during the step of forming said source and drain regions along with said polysilicon layer portion located over said shallow semiconductor region of opposite conductivity type to render both said polysilicon layer portions electrically conductive, said electrically conductive polysilicon layer portion located over said shallow semiconductor region of opposite conductivity type being one plate of the semiconductor capacitor device, the portion of said insulating layer located over said region of opposite conductivity type being the dielectric of said semiconductor capacitor device, and said region of opposite conductivity type being the other plate of said semiconductor capacitor device.
Claim 3
Dependent Claim
52 words
A method in accordance with claim 1 wherein said step of forming said semiconductor substrate region of one conductivity type within a higher resistivity semiconductor substrate region of the same type conductivity comprising ion implanting impurities of said one conductivity type into said higher resistivity semiconductor region of said one conductivity type.
Claim 4
Dependent Claim
51 words
A method in accordance with claim 1 wherein said step of forming said shallow semiconductor substrate region of opposite conductivity type comprising ion implanting impurities of said opposite conductivity type into said semiconductor region of one conductivity type located within said higher resistivity semiconductor substrate region of said one conductivity type.
Claim 5
Dependent Claim
22 words
A method in accordance with claim 1 wherein said step of forming said insulating layer comprising thermally growing a silicon dioxide layer.
Claim 6
Dependent Claim
37 words
A method in accordance with claim 1 wherein one of said source and drain regions of said MOS semiconductor device being in contact with said semiconductor substrate region of opposite type conductivity of said semiconductor capacitor device.
Claim 7
Dependent Claim
169 words
A method in accordance with claim 1 wherein said step of forming said semiconductor region of one conductivity type within a higher resistivity semiconductor region of the same type conductivity comprising ion implanting impurities of said one conductivity type into said higher resistivity semiconductor region of said one conductivity type, said step of forming said shallow semiconductor substrate region of opposite conductivity type comprising ion implanting impurities of said opposite conductivity type into said semiconductor region of one conductivity type located within said higher resistivity semiconductor region of said one conductivity type, said ion implanted impurities forming said semiconductor substrate region of one conductivity type being boron ions, said ion implanted impurities forming said shallow semiconductor substrate region of opposite conductivity type being arsenic ions, said step of forming said insulating layer comprising thermally growing a silicon dioxide layer, and one of said source and drain regions of said MOS semiconductor device being in contact with said semiconductor substrate region of opposite type conductivity of said semiconductor capacitor device.
Claim 8
Dependent Claim
51 words
A method in accordance with claim 2 wherein said step of forming said shallow semiconductor substrate region of opposite conductivity type comprising ion implanting impurities of said opposite conductivity type into said semiconductor region of one conductivity type located within said higher resistivity semiconductor substrate region of said one conductivity type.
Claim 9
Dependent Claim
15 words
A method in accordance with claim 2 wherein said ion implanted impurities being boron ions.
Claim 10
Dependent Claim
15 words
A method in accordance with claim 3 wherein said ion implanted impurities being arsenic ions.
Claim 11
Dependent Claim
39 words
A method in accordance with claim 7 wherein said ion implanted impurities forming said semiconductor region of one conductivity type being boron ions, said ion implanted impurities forming said shallow semiconductor region of opposite conductivity type being arsenic ions.
Claim 12
Independent Claim
276 words
A method for making an integrated semiconductor structure having an MOS semiconductor device and a semiconductor capacitor device comprising the steps of: forming a semiconductor region of one conductivity type within a higher resistivity semiconductor substrate region of the same type conductivity, forming a shallow semiconductor region of opposite conductivity type having at least one portion thereof located within said semiconductor region of one conductivity type located within said higher resistivity semiconductor substrate region of the same one type conductivity, forming an insulating layer on a surface of said semiconductor region of one conductivity type, said higher resistivity semiconductor substrate region of the same one type conductivity, and said shallow semiconductor region of opposite conductivity type, forming spaced polysilicon layer portions on the surface of said insulating layer at least over said shallow semiconductor region of opposite conductivity type and over a portion of said higher resistivity semiconductor substrate region of said one conductivity type spaced from said shallow semiconductor region of opposite conductivity type to be used as a self-aligned polysilicon gate electrode for the MOS semiconductor device, forming at least one active region for the MOS semiconductor device using said polysilicon gate electrode layer portion as a self-aligned mask which is doped during the step of forming said active region, said electrically conductitve polysilicon layer portion located at least over said shallow semiconductor region of opposite conductivity type being one plate of the semiconductor capacitor device, the portion of said insulating layer located over said region of opposite conductivity type being the dielectric of said semiconductor capacitor device, and said region of opposite conductivity type being the other plate of said semiconductor capacitor device.
Claim 13
Independent Claim
276 words
A method for making an integrated semiconductor structure having an MOS semiconductor device and a semiconductor capacitor device comprising the steps of: forming a semiconductor region of one conductivity type within a higher resistivity semiconductor substrate region of the same type conductivity, forming a shallow semiconductor region of opposite conductivity type having at least one portion thereof located within said semiconductor region of one conductivity type located within said higher resistivity semiconductor substrate region of the same one type conductivity, forming an insulating layer on a surface of said semiconductor region of one conductivity type, said higher resistivity semiconductor substrate region of the same one type conductivity, and said shallow semiconductor region of opposite conductivity type, forming spaced polysilicon layer portions on the surface of said insulating layer at least over said shallow semiconductor region of opposite conductivity type and over a portion of said higher resistivity semiconductor substrate region of said one conductivity type spaced from said shallow semiconductor region of opposite conductivity type to be used as a self-aligned polysilicon gate electrode for the MOS semiconductor device, forming at least one active region for the MOS semiconductor device using said polysilicon gate electrode layer portion as a self-aligned mask which is doped during the step of forming said active region, said electrically conductitve polysilicon layer portion located at least over said shallow semiconductor region of opposite conductivity type being one plate of the semiconductor capacitor device, the portion of said insulating layer located over said region of opposite conductivity type being the dielectric of said semiconductor capacitor device, and said region of opposite conductivity type being the other plate of said semiconductor capacitor device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-21 | 1985-03-23 | 1985-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-21 | 1989-03-23 | 1989-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-21 | 1993-03-23 | 1993-09-22 | $7700.00 | Window Closed / Lapsed |