Abstract A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, digit and FLAG mask decoders, key input logic, a register and FLAG data storage array, a decimal and FLAG arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.
In data processing apparatus, data storage means in the form of an array of rows and columns of memory cells arranged in N columns with N cells in each row, where N is an integer greater than two, means for repeatedly generating N timed address signals in a given time period for addressing columns of the cells in sequence, means for generating output timing signals recurring once for each complete sequence of N address signals, means for providing coded representations of the address signals and of the output timing signals, means for detecting coincidence between the coded representation of the address signals and the coded representation of the output timing signals to produce coincidence signals, and means responsive to the coincidence signals for causing data to be read out of the data storage means into output means.
Claim 2
Dependent Claim
137 words
In data processing apparatus, data storage means in the form of an array of rows and columns of memory cells arranged in N columns with N cells in each row, where N is an integer greater than two, means for repeatedly generating N timed address signals in a given time period for addressing columns of the cells in sequence, means for generating output timing signals recurring once for each complete sequence of N address signals, means for providing coded representations of the address signals and of the output timing signals, means for detecting coincidence between the coded representation of the address signals and the coded representation of the output timing signals to produce coincidence signals, and means responsive to the coincidence signals for causing data to be read out of the data storage means into output means.
Claim 3
Dependent Claim
27 words
In data processing apparatus according to claim 1, the means for generating output timing signals producing a complete sequence of output timing signals in N(N-1) time periods.
Claim 4
Dependent Claim
41 words
In data processing apparatus according to claim 2, the data storage means being organized in a plurality of multi-digit registers and the cells a given register being addressed in an order of the least significant digit to the most significant digit.
Claim 5
Dependent Claim
23 words
In data processing apparatus occording to claim 3, the coincidence signals accurring in an order of most significant digit to least significant digit.