US3704454A — Accessing system for and in integrated circuit ty…

Claim 1

Independent Claim 292 words

In a digital data, integrated circuit memory, using field effect components or MOS type and structure there being sources of alternating first and second phase signals, the combination comprising: a. a plurality of decoder drivers, each including first means at substrate potential, first and second drain electrodes at the channel means and separated and insulated from each other and from the source electrode means except for conduction through the channel means, and gate electrode means disposed for controlling conduction through the channel means, therebeing means to apply an addressing signal to the gate electrode means; a first minimum size FET transistor connected with drain and source path between the first drain electrode and the first phase signal source; a second minimum size FET transistor connected between the second phase signal and the gate of the first transistor and establishing therewith a node; a third minimum Size FET transistor connected with source drain path between the second drain electrode and second node, and having its gate connected to the first signal source; a capacitor connected to the node, further connected to receive signal derived from the first phase signal source; b. a plurality of decoder transistors including a fourth minimum size FET transistor having its gate connected to said first drain electrode or one of the drivers of the plurality; and operated for conduction during first phase signal; c. a plurality of memory locations including at least one FET having its gate connected to said fourth minimum size FET to be rendered conductive in dependence upon the state of conduction of the fourth transistor during a first phase signal; and circuit means connected to derive a read out signal from the memory locations in dependence upon the states of conductions said FET''s therein.

Claim 2

Dependent Claim 292 words

In a digital data, integrated circuit memory, using field effect components or MOS type and structure there being sources of alternating first and second phase signals, the combination comprising: a. a plurality of decoder drivers, each including first means at substrate potential, first and second drain electrodes at the channel means and separated and insulated from each other and from the source electrode means except for conduction through the channel means, and gate electrode means disposed for controlling conduction through the channel means, therebeing means to apply an addressing signal to the gate electrode means; a first minimum size FET transistor connected with drain and source path between the first drain electrode and the first phase signal source; a second minimum size FET transistor connected between the second phase signal and the gate of the first transistor and establishing therewith a node; a third minimum Size FET transistor connected with source drain path between the second drain electrode and second node, and having its gate connected to the first signal source; a capacitor connected to the node, further connected to receive signal derived from the first phase signal source; b. a plurality of decoder transistors including a fourth minimum size FET transistor having its gate connected to said first drain electrode or one of the drivers of the plurality; and operated for conduction during first phase signal; c. a plurality of memory locations including at least one FET having its gate connected to said fourth minimum size FET to be rendered conductive in dependence upon the state of conduction of the fourth transistor during a first phase signal; and circuit means connected to derive a read out signal from the memory locations in dependence upon the states of conductions said FET''s therein.

Claim 3

Dependent Claim 73 words

In a memory as in claim 1, the fourth transistor connected in series with electrode plating means serving as gates for a plurality of FET''s pertaining to different memory locations, each FET of the latter plurality connected to a different one of a plurality of sources of drain potential and means connected to control the potential of the source in dependence upon the first phase signal and selectively for each of the sources.

Claim 4

Dependent Claim 43 words

In a memory as in claim 2, the sources of drain potential being nodes, connected to be charged in response to each second phase signal, the circuit means connected to sense the charge state of the latter nodes during each first phase signal.

Claim 5

Dependent Claim 51 words

In a memory as in claim 1, the decoder transistors of the plurality connected in series to each other and to the source of first phase signals, each decoder transistor connected with its gate to one of the decoder driver, to operate a gating bus for the plurality of memory locations.

Claim 6

Dependent Claim 102 words

In a memory as in claim 1, including a second plurality of decoder transistors including a fifths transistor operated for conduction during first phase signals further including a second plurality of decoder drivers each constructed similar to the drivers of the first plurality and having their respective gate electrode means respectively connected to the first drain electrode of one of the drivers of the first plurality, and having its first drain electrode connected to the fifths transistor of the second plurality of decoder transistor, the fifths transistor rendered conductive when the fourth transistor is non-conductive during first phase signals and vice versa.

Claim 7

Dependent Claim 236 words

In a read only integrated circuit memory using field effect components of MOS type and structure, there being sources of alternating first and second phase signals in immediate sequence for clocking and phasing operation of the memory, the combination comprising a plurality of gate electrodes establishing rows of a matrix; a plurality of drain electrode establishing zones defining columns of a matrix, intersecting the rows of the matrix; source electrode means in physical association with each drain electrode means of the plurality, extending alongside thereof and provided to establish FET''s respectively in some of said intersections, and in representation of bits of a first value to be stored in those intersections, absence of a FET in the remaining intersections establishing bits of opposite value therein; first means for establishing substrate potential in each of the rows during second phase signals; second means for establishing at least one node and including means for charging the node in isolation from substrate potential during second phase signals; third means for coupling a selected one of the columns to the node during second phase signals; fourth means for providing gating potential in a selected one of the rows during first phase signals, to obtain discharge of the node if a FET is established in the intersection of the selected row and of the selected column; and fifth meanS for providing substrate potential directly to all of said source electrode means.

Claim 8

Dependent Claim 236 words

In a read only integrated circuit memory using field effect components of MOS type and structure, there being sources of alternating first and second phase signals in immediate sequence for clocking and phasing operation of the memory, the combination comprising a plurality of gate electrodes establishing rows of a matrix; a plurality of drain electrode establishing zones defining columns of a matrix, intersecting the rows of the matrix; source electrode means in physical association with each drain electrode means of the plurality, extending alongside thereof and provided to establish FET''s respectively in some of said intersections, and in representation of bits of a first value to be stored in those intersections, absence of a FET in the remaining intersections establishing bits of opposite value therein; first means for establishing substrate potential in each of the rows during second phase signals; second means for establishing at least one node and including means for charging the node in isolation from substrate potential during second phase signals; third means for coupling a selected one of the columns to the node during second phase signals; fourth means for providing gating potential in a selected one of the rows during first phase signals, to obtain discharge of the node if a FET is established in the intersection of the selected row and of the selected column; and fifth meanS for providing substrate potential directly to all of said source electrode means.

Claim 9

Dependent Claim 53 words

In a read-only memory as in claim 6, the third means operated to couple the node to a plurality of the columns from which the selection is taken during and in response to a second phase signal, and to discouple the node from the non-selected columns in response to the succeeding first signal.

Claim 10

Dependent Claim 108 words

In a read-only memory as in claim 7, the third means including a plurality of decoder FET''s serially connected between the node and a column of the plurality, means establishing a second node and connected to be charged during second phase signals, a decoder FET of the plurality having its gate controlled in response to the charge on the second node; a capacitor connected to the gate to apply thereto the first phase signal to augment gating control for the decoder FET by the second node as charged; and means to selectively discharge or inhibit discharge of the second node during and in response to first phase signals.

Claim 11

Dependent Claim 125 words

In a read-only memory as in claim 6, the fourth means including a plurality of decoder FET''s, serially connected between the source of the first phase signals and a row of the plurality, a decoder FET of the plurality having its gate serially connected to a control FET which, in turn, is connected to the source of first phase signals; means establishing a second node connected to be charged in response to second phase signals, the gate of the control FET connected to that second node, a capacitor connected between the second node and the source of first phase signals; and means responsive to an addressing signal to selectively discharge or inhibit discharge of the second node during and in response to first phase signals.

Claim 12

Dependent Claim 190 words

In an integrated circuit memory with field effect components of the insulated gate type, there being sources to provide trains of alternating first and second phase pulses in immediate sequence, the memory responding to addressing signals, the combination comprising: means establishing a plurality of nodes connected to be periodically charged by the second phase pulses; first plurality of FET means each serially connected between a source of substrate potential and one of the plurality of nodes, each further connected to be responsive to an addressing signal and a first phase pulse to selectively discharge or inhibit discharge of the node; second plurality of FET means each connected to be controlled in response to first phase pulses, respectively to the charge state of one of the nodes and to the respective addressing signal, to provide a plurality of output signals; and circuit means in the integrated circuit, including a plurality of serially interconnected decoder FET''s, each having its gate connected respectively to receive one of said output signals so as to provide memory addressing during first phase signals in dependence upon the output signal as controlled by the second FET means.

Claim 13

Dependent Claim 190 words

In an integrated circuit memory with field effect components of the insulated gate type, there being sources to provide trains of alternating first and second phase pulses in immediate sequence, the memory responding to addressing signals, the combination comprising: means establishing a plurality of nodes connected to be periodically charged by the second phase pulses; first plurality of FET means each serially connected between a source of substrate potential and one of the plurality of nodes, each further connected to be responsive to an addressing signal and a first phase pulse to selectively discharge or inhibit discharge of the node; second plurality of FET means each connected to be controlled in response to first phase pulses, respectively to the charge state of one of the nodes and to the respective addressing signal, to provide a plurality of output signals; and circuit means in the integrated circuit, including a plurality of serially interconnected decoder FET''s, each having its gate connected respectively to receive one of said output signals so as to provide memory addressing during first phase signals in dependence upon the output signal as controlled by the second FET means.

Claim 14

Dependent Claim 73 words

In a memory as in claim 10, the state of conduction of the decoder FET''s of the plurality controlling the potential of an electrode means serving as plurality of gates respectively for a plurality of memory element FET''s, to be rendered selectively conductive during first phase signals, the gates conductively decoupled from substrate potential during first phase signals, at least when receiving potential for selective conductivity control of memory FET''s of the plurality.

Claim 15

Dependent Claim 60 words

In a memory as in claim 11, each of the FET means of the second plurality including a FET connected with its source-drain channel serially to the source of first phase signals to provide the output signal and having its gate connected to the node, there being a capacitor connected between the node and the source of first phase signals.

Claim 16

Dependent Claim 212 words

In an integrated circuit memory with field effect components of the insulated gate type, there being sources to provide trains of alternating first and second phase pulses in immediate sequence, the memory responding to addressing signals, the combination comprising: a plurality of memory locations including at least one FET and having its gate connected to receive gating potential for accessing the location having the FET; a plurality of decoder FET''s serially connected to each other and between the gate of the memory FET and the source of first phase signals; a control circuit for each decoder FET, and including a control FET having its drain-source path connected between the source of first phase signals and the gate of the respective decoder FET; means establishing a node connected to the gate of the control FET; a capacitor connected between the node and the source of first phase signals; means connected for charging the node during and in response to second phase signals; and means connected for selectively charging and discharging the node during and in response to first phase signals, the selectivity being under control of a memory addressing signal, the node when remaining charged during first phase signals rendering the control FET conductive, which, in turn, renders the respective decoder FET conductive.

Claim 17

Dependent Claim 212 words

In an integrated circuit memory with field effect components of the insulated gate type, there being sources to provide trains of alternating first and second phase pulses in immediate sequence, the memory responding to addressing signals, the combination comprising: a plurality of memory locations including at least one FET and having its gate connected to receive gating potential for accessing the location having the FET; a plurality of decoder FET''s serially connected to each other and between the gate of the memory FET and the source of first phase signals; a control circuit for each decoder FET, and including a control FET having its drain-source path connected between the source of first phase signals and the gate of the respective decoder FET; means establishing a node connected to the gate of the control FET; a capacitor connected between the node and the source of first phase signals; means connected for charging the node during and in response to second phase signals; and means connected for selectively charging and discharging the node during and in response to first phase signals, the selectivity being under control of a memory addressing signal, the node when remaining charged during first phase signals rendering the control FET conductive, which, in turn, renders the respective decoder FET conductive.

Claim 18

Dependent Claim 67 words

In a memory as in claim 13, the memory FET established between first and second zones underneath its gate defined as electrode plating and as connected to the decoder FET''s, the first zone connected to receive substrate potential, the second zone selectively connected to an output node during and in response to first phase signals, the output node connected to be charged during each second phase signal.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1975-11-28	1976-05-29	1976-11-28	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1979-11-28	1980-05-29	1980-11-28	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1983-11-28	1984-05-29	1984-11-28	$7700.00	Window Closed / Lapsed

Accessing system for and in integrated circuit type memories

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