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US4290111A
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Decibel addition circuit
Assignee: Singer Co
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Filing: 1979-12-12
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Granted: 1981-09-15
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Expires: 1999-12-12
Abstract
Abstract An addition circuit for adding two decibel measurements received at input terminals 12 and 14, first substracts the inputs in a subtractor circuit 16 to obtain a difference d. Then, based upon the magnitude of the difference d, the addition circuit determines the value of 10 log [1+10 d/10 ] or 20 log [1+10 d/20 ] in a read-only memory circuit 20. A selector circuit 24 determines which of the two input decibel measurements is the larger and controls the complementer circuit 18 so that the value of the difference d is always negative. The output of the read-only memory circuit 20 is added to the larger of the two input in an adder 22.
Inventors
- 👤 Keith Dillon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:11
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F7/4833; G06F1/00; G06F1/02; G06F1/03; G06F1/0307
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
91 words
A decibel addition circuit for adding two signals in the decibel form of measurement directly, comprising: means for determining which of said two signals is the larger, means for determining the difference in magnitude between said two signals, means responsive to said difference in magnitude for generating a signal having a value of 10 log [1+10 d/10 ], and means for adding said signal generated by said last-mentioned means to the larger of said two signals determined by said first-mentioned means for providing the decibel sum of said two decibel signals.
Claim 2
Dependent Claim
91 words
A decibel addition circuit for adding two signals in the decibel form of measurement directly, comprising: means for determining which of said two signals is the larger, means for determining the difference in magnitude between said two signals, means responsive to said difference in magnitude for generating a signal having a value of 10 log [1+10 d/10 ], and means for adding said signal generated by said last-mentioned means to the larger of said two signals determined by said first-mentioned means for providing the decibel sum of said two decibel signals.
Claim 3
Dependent Claim
25 words
A decibel addition circuit according to claim 1 wherein said means for determining the difference in magnitude between said two signals includes subtractor circuit means.
Claim 4
Dependent Claim
22 words
A decibel addition circuit according to claim 1 wherein said means responsive to said difference in magnitude includes a read-only memory circuit.
Claim 5
Dependent Claim
18 words
A decibel addition circuit according to claim 1 wherein said means for adding includes an adder circuit means.
Claim 6
Dependent Claim
45 words
A decibel addition circuit according to claim 2 including selector circuit means connected with said means for determining the difference in magnitude between said two signals for selecting the larger of said two signals, so that the smaller signal is subtracted from the larger signal.
Claim 7
Dependent Claim
51 words
A decibel addition circuit according to claim 2 including complementer circuit means connected to said subtractor circuit means, and selector circuit means to determine which of the two signals is the larger and connected to control said complementer circuit means, so that the value of said difference is a predetermined sign.
Claim 8
Dependent Claim
25 words
A decibel addition circuit according to claim 1 wherein said means for determining which of said two signals is the larger includes multiplexer circuit means.
Claim 9
Dependent Claim
22 words
A decibel addition circuit according to claim 1 wherein said means responsive to said difference in magnitude includes logarithmic conversion circuit means.
Claim 10
Dependent Claim
18 words
A decibel addition circuit according to claim 8 wherein said logarithmic conversion means comprises a read-only memory circuit.
Claim 11
Dependent Claim
36 words
A decibel addition circuit according to claim 5 including complementer circuit means connected between said subtractor circuit means and said read-only memory circuit means to develop the modulus of the output from the subtractor circuit means.
References Cited (Backward Citations)
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US3792246A
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US3940603A
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US4011509A
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US4000463A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-14 | 1985-03-16 | 1985-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-14 | 1989-03-16 | 1989-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-14 | 1993-03-16 | 1993-09-15 | $7700.00 | Window Closed / Lapsed |