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Patent US4290015A successfully refreshed from Google Patents.
US4290015A
Expired / Lapsed
US
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Electrical validator for a printed circuit board test fixture and a method of validation thereof
Assignee: National Semiconductor Corp
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Filing: 1979-10-18
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Granted: 1981-09-15
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Expires: 1999-10-18
Abstract
Abstract This invention relates to a structure for testing the integrity of a printed circuit board test fixture and to a method for implementing the verification of the fixture.
Inventors
- 👤 Donald J. Labriola
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:17
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2801; G01R31/2806; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/07364; G01R1/07378
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
141 words
A structure for validating the performance of a test fixture for a test system for printed circuit boards, the structure comprising: a board having (1) an electrically conductive sheet on a first region of a surface of the board and (2) a plurality of electrically conductive pads on a second region of the surface, the pads electrically isolated from each other and from the sheet, the board having no transistors formed on it; and a test module having (1) a like plurality of first output leads corresponding on a one-to-one basis to the pads, each first lead attached to the corresponding pad, (2) a second output lead attached to the sheet, and (3) a like plurality of impedance elements corresponding on a one-to-one basis to the first leads, each impedance element connected between the second lead and the corresponding first lead.
Claim 2
Dependent Claim
141 words
A structure for validating the performance of a test fixture for a test system for printed circuit boards, the structure comprising: a board having (1) an electrically conductive sheet on a first region of a surface of the board and (2) a plurality of electrically conductive pads on a second region of the surface, the pads electrically isolated from each other and from the sheet, the board having no transistors formed on it; and a test module having (1) a like plurality of first output leads corresponding on a one-to-one basis to the pads, each first lead attached to the corresponding pad, (2) a second output lead attached to the sheet, and (3) a like plurality of impedance elements corresponding on a one-to-one basis to the first leads, each impedance element connected between the second lead and the corresponding first lead.
Claim 3
Dependent Claim
24 words
A structure as in claim 1 wherein each impedance element is a resistor, the board having no capacitive or inductive elements formed on it.
Claim 4
Dependent Claim
46 words
A structure as in claim 2 wherein the resistance of one of the resistors is at the high resistance range of operation of the test system and the resistance of another of the resistors is at the low resistance range of operation of the test system.
Claim 5
Dependent Claim
18 words
A structure as in claim 3 wherein the board has holes therethrough filled with an electrically conductive material.
Claim 6
Dependent Claim
34 words
A structure as in claim 4 wherein each hole corresponds to a contact probe of the test fixture, the material in each hole placed in intended contact with the corresponding probe during test operation.
Claim 7
Dependent Claim
16 words
A structure as in claim 1, 2, 3, 4, or 5 wherein the plurality is two.
Claim 8
Independent Claim
96 words
A method of validating a printed circuit board test fixture having contact probes to ensure proper operation of the test fixture comprising the steps of: placing each probe in intended contact with a board having an electrically conductive sheet on a surface thereof but having no transistors formed thereon; sequentially passing an electrical signal through each probe, the sheet, and a selected known impedance to measure the impedance to passage of the signal; and comparing the measured impedance to an expected impedance, thereby to provide an indication of whether the probe is properly conducting the signal.
Claim 9
Independent Claim
96 words
A method of validating a printed circuit board test fixture having contact probes to ensure proper operation of the test fixture comprising the steps of: placing each probe in intended contact with a board having an electrically conductive sheet on a surface thereof but having no transistors formed thereon; sequentially passing an electrical signal through each probe, the sheet, and a selected known impedance to measure the impedance to passage of the signal; and comparing the measured impedance to an expected impedance, thereby to provide an indication of whether the probe is properly conducting the signal.
Claim 10
Dependent Claim
25 words
A method as in claim 7 wherein the impedance measurement is made by a voltage reading of the sheet during the passage of the signal.
Claim 11
Dependent Claim
53 words
A method as in claim 8 wherein the board has a pair of electrically conductive pads connected through a pair of resistance elements, respectively, to the sheet, each pad electrically connectable to each probe through a corresponding conductively filled hole through the board, the known impedance selectively comprising each of the resistance elements.
References Cited (Backward Citations)
US4115735A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-14 | 1985-03-16 | 1985-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-14 | 1989-03-16 | 1989-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-14 | 1993-03-16 | 1993-09-15 | $7700.00 | Window Closed / Lapsed |