Forced commutated starting circuit for load commutated inverter drive system

Claim 1

In an inverter polyphase synchronous machine drive system including a polyphase synchronous machine excited from a source of direct current potential by an inverter, said inverter providing forced machine commutation for initial excitement thereof, said inverter comprising: a plurality of pairs of serially-connected unidirectional conduction means corresponding in number to the number of machine phases, each pair of said conduction means connected across said source of direct current potential and coupled at the pair junction to a corresponding machine phase, respectively, each said conduction means controlling current therein in response to a gate control signal impressed thereon; first and second controlled bidirectional conduction means serially connected across said source of direct current potential, each said controlled bidirectional conduction means conducting current in a direction determined by an external gate signal impressed thereon; capacitor means connected between the junction of said first and second controlled bidirectional conduction means and the neutral terminal of said polyphase machine; means for determining the charge of said capacitor; and means for providing gate control signals to each of said unidirectional conduction means and each of said bidirectional current means to cause current to flow in a predetermined sequence through said machine phases with energy supplied by said capacitor, when said capacitor charge is above a predetermined value and for providing gate control signals to each of said unidirectional conduction means and each of said bidirectional current means to cause current to flow in said predetermined sequence through said machine phases and to charge said capacitor, with energy supplied by said source of DC potential when said capacitor charge is below a predetermined value.

Claim 6

A method of sequencing three main pairs of unidirectional switch means during forced commutation of a 3 phase bridge inverter supplying 3 phase power to a star connected load, said inverter having auxiliary switch means appropriately conducting during each of the following steps to provide a complete current path through a phase of said load, the method comprising the consecutive steps of: (a) Switching the upper switch means in the first main pair on while switching the lower switch means in the third main pair off; (b) Switching the lower switch means in the third main pair on while switching the upper switch means in the first main pair off; (c) Repeating step a followed by step b a plurality of times, the number of repetitions being dependent upon the desired period of the current supplied to said load; (d) Switching the lower switch means in the third main pair on while switching the upper switch means in the second main pair off; (e) Switching the upper switch means in the second main pair on while switching the lower switch means in the third main pair off; (f) Repeating step d followed by step e a plurality of times, the number of repetitions being dependent upon the desired period of the current supplied to said load; (g) Switching the upper switch means in the second main pair on while switching the lower switch means in the first main pair off; (h) Switching the lower switch means in the first main pair on while switching the upper switch means in the second main pair off; (i) Repeating step g followed by step h a plurality of times, the number of repetitions being dependent upon the desired period of the current supplied to said load; (j) Switching the lower switch means in the first main pair on while switching the upper switch means in the third main pair off; (k) Switching the upper switch means in the third main pair on while switching the lower switch means in the first main pair off; (l) Repeating step j followed by step k a plurality of times, the number of repetitions being dependent upon the desired period of the current supplied to said load; (m) Switching the upper switch means in the third main pair on while switching the lower switch means in the second main pair off; (n) Switching the lower switch means in the second main pair on while switching the upper switch means in the third main pair off; (o) Repeating step m followed by step n a plurality of times, the number of repetitions being dependent upon the desired period of current supplied to said load; (p) Switching the lower switch means in the second main pair on while switching the lower switch means in the second main pair off; (q) Switching the upper switch means in the first main pair on while switching the lower switch means in the second main pair off; (r) Repeating steps a-r.

Claim 7

A method of sequencing three main pairs of unidirectional switch means during forced commutation of a 3 phase bridge inverter supplying 3 phase power to a star connected load, said inverter having auxiliary switch means appropriately conducting during each of the following steps to provide a complete current path through a phase of said load, the method comprising the consecutive steps of: (a) Switching the upper switch means in the first main pair on while switching the lower switch means in the third main pair off; (b) Switching the lower switch means in the third main pair on while switching the upper switch means in the first main pair off; (c) Repeating step a followed by step b a plurality of times, the number of repetitions being dependent upon the desired period of the current supplied to said load; (d) Switching the lower switch means in the third main pair on while switching the upper switch means in the second main pair off; (e) Switching the upper switch means in the second main pair on while switching the lower switch means in the third main pair off; (f) Repeating step d followed by step e a plurality of times, the number of repetitions being dependent upon the desired period of the current supplied to said load; (g) Switching the upper switch means in the second main pair on while switching the lower switch means in the first main pair off; (h) Switching the lower switch means in the first main pair on while switching the upper switch means in the second main pair off; (i) Repeating step g followed by step h a plurality of times, the number of repetitions being dependent upon the desired period of the current supplied to said load; (j) Switching the lower switch means in the first main pair on while switching the upper switch means in the third main pair off; (k) Switching the upper switch means in the third main pair on while switching the lower switch means in the first main pair off; (l) Repeating step j followed by step k a plurality of times, the number of repetitions being dependent upon the desired period of the current supplied to said load; (m) Switching the upper switch means in the third main pair on while switching the lower switch means in the second main pair off; (n) Switching the lower switch means in the second main pair on while switching the upper switch means in the third main pair off; (o) Repeating step m followed by step n a plurality of times, the number of repetitions being dependent upon the desired period of current supplied to said load; (p) Switching the lower switch means in the second main pair on while switching the lower switch means in the second main pair off; (q) Switching the upper switch means in the first main pair on while switching the lower switch means in the second main pair off; (r) Repeating steps a-r.