Beam deflection method and apparatus for sector scan ultrasound imaging systems

Claim 3

A method as claimed in claim 1, wherein said stored delay time data is represented by M data bits, and said accumulated data is represented by (M+K) data bits where K is a binary number of (N-1) and said output data is represented by the higher significant M data bits of said accumulated data.

Claim 4

A method as claimed in claim 2, wherein said M data bits stored in said memory are a binary representation of the total delay times of said transducer elements.

Claim 5

A method as claimed in claim 1, further comprising the steps of: storing a plurality of sets of data in a second memory, each datum corresponding to each said transducer elements and each set corresponding to each deflection angle of said ultrasound beam, each said datum representing an additional delay time to be added to the first-mentioned delay time for converging said ultrasound beam; successively retrieving each said datum from said second memory; repeatedly accumulating the retrieved data for generating an output data in succession; and adding the last-mentioned, successively generated output data to the first-mentioned, successively generated output data.

Claim 6

A method as claimed in claim 4, wherein each of said data stored in said second memory comprises a first data representing a time delay and a second data representing the plus or minus sign for adding or subtracting respectively said first data to or from the accumulated first data.

Claim 7

Apparatus for successively deflecting an ultrasound beam emanating from an array of piezoelectric transducer elements at different angles in discrete steps by successively activating said transducer elements at delayed timing, comprising: means for generating low frequency timing pulses timed to correspond to each said deflecting angle of said beam and high frequency timing pulses corresponding in number to said transducer elements to be activated in response to said beam being deflected at each said angle; a memory in which is stored a plurality of delay time data, each datum representing a binary number corresponding to the delay time between said successively activated transducer elements for each said deflection angle; means for retrieving each said datum from said memory in response to said low frequency timing pulse; means for repeatedly accumulating said retrieved data in response to said high frequency timing pulse; a plurality of counters corresponding to said transducer elements, the count values of said counters being presettable in accordance with an output data from said accumulating means; means for successively enabling said counters to permit same to be preset to said output data in response to said high frequency timing pulses; and means for supplying count pulses to said counters for successively activating said transducer elements in response to each said preset count values being reached.

Claim 8

Apparatus for successively deflecting an ultrasound beam emanating from an array of piezoelectric transducer elements at different angles in discrete steps by successively activating said transducer elements at delayed timing, comprising: means for generating low frequency timing pulses timed to correspond to each said deflecting angle of said beam and high frequency timing pulses corresponding in number to said transducer elements to be activated in response to said beam being deflected at each said angle; a memory in which is stored a plurality of delay time data, each datum representing a binary number corresponding to the delay time between said successively activated transducer elements for each said deflection angle; means for retrieving each said datum from said memory in response to said low frequency timing pulse; means for repeatedly accumulating said retrieved data in response to said high frequency timing pulse; a plurality of counters corresponding to said transducer elements, the count values of said counters being presettable in accordance with an output data from said accumulating means; means for successively enabling said counters to permit same to be preset to said output data in response to said high frequency timing pulses; and means for supplying count pulses to said counters for successively activating said transducer elements in response to each said preset count values being reached.

Claim 9

Apparatus as claimed in claim 6, wherein each said datum is a binary representation of the total delay times of said transducer elements.

Claim 10

Apparatus as claimed in claim 6, wherein each said datum is a binary representation of (d sin θ/C)×(N-1/Q), where d is the center-to-center spacing between successive ones of said transducer elements, θ is said angle of deflection, C, the velocity of acoustic energy propagating through a body under investigation, N, the number of said transducer elements, and Q, a unit delay time.

Claim 11

Apparatus as claimed in claim 8, wherein said unit delay time is a minimum delay time between said successively activated transducer elements.

Claim 12

Apparatus as claimed in claim 8, wherein said unit delay time is a unit quantization time required to generate a single data bit.

Claim 13

Apparatus as claimed in claim 6, wherein said repeatedly accumulating means comprises a digital adder having first input terminals connected to receive said retrieved differential time data and second input terminals, and a latch connected to receive an output data from said adder for latching the received data and applying said latched data to said second input terminals of said adder in response to said high frequency timing pulse, the data output of said latch being connected to the preset input terminals of each of said counters.

Claim 14

Apparatus as claimed in claim 8, wherein each of said delay time datum is represented by M data bits and wherein said accumulating means comprises (M+K) data bits where K is a binary number of (N-1), the data bits delivered from said accumulating means to said counters being the higher M data bits thereof.

Claim 15

Apparatus as claimed in claim 6 or 12, further comprising a second memory in which is stored plural sets of beam convergence data bits, said data bits corresponding in number of said transducer elements and each set corresponding to each deflection angle of said beam, each of said convergence data bit representing an additional delay time for converging said ultrasound beam, said second memory further storing plus and minus sign data bits, means for retrieving each of said data bits and one of said sign data bits from said second memory in response to said high frequency timing pulse, means for repeatedly adding said retrieved convergence data bit from said second memory in response to said high frequency timing pulses in the presence of said retrieved plus sign data bit or repeatedly subtracting the retrieved convergence data bit from the added data bits in response to said high frequency timing pulses in the presence of the retrieved minus sign data bit, and means for adding an output data from said adding-and-subtracting means to the output data from said accumulating means.

Claim 16

Apparatus as claimed in claim 13, adapted for use in an ultrasound probe system including beam transmit and receive units, wherein second memory comprises a plurality of memory sections each storing plural sets of beam convergence data bits and plus and minus sign data bits, means for selectively connecting the stored data in said memory sections to said adding-and-subtracting means and to second adding-and-subtracting means constructed identically to the first-mentioned adding-and-subtracting means, and second adding means for adding an output data from said second adding-and-subtracting means to the output data from said accumulating means for providing a combined output data to the receive unit of said system.

Claim 17

Apparatus as claimed in claim 13, wherein said adding-and-subtracting means comprises a digital adder having a first set of input terminals connected to said memory, a second set of input terminals and a sign input terminal for permitting said digital adder to act as an adder or a subtractor depending on said sign data bits applied thereto from said second memory, and a latch receptive of an output data from said digital adder for applying the latched data to said second set of input terminals of said adder, an output data from said latch being the output data of said adding-and-subtracting means.

Claim 18

Apparatus as claimed in claim 13, further comprising a second memory in which is stored plural sets of beam convergence data bits, said data bits corresponding in number to said transducer elements and each set corresponding to each deflection angle of said beam, each of said convergence data bit representing an additional differential time for converging said ultrasound beam, said second memory further storing plus and minus sign data bits, means for retrieving each of said data bit and one of said sign data bits from said second memory in response to said high frequency timing pulse, means for repeatedly adding said retrieved convergence data bit from said second memory in response to said high frequency timing pulses in the presence of said retrieved plus sign data bit or repeatedly subtracting the retrieved convergence data bit from the added data bits in response to said high frequency timing pulses in the presence of the retrieved minus sign data bit, and means for adding an output data from said adding-and-subtracting means to the output data from said accumulating means, wherein the last-mentioned adding means is identically constructed to said accumulating means and wherein the output data from said adding-and-subtracting means is added to the N-1) data bits of said last-mentioned adding means.

Claim 19

Apparatus as claimed in claim 16, wherein said adding-and-subtracting means comprises a digital adder having a first set of input terminals connected to said second memory, a second set of input terminals and a sign input terminal for permitting said digital adder to act as an adder or a subtractor depending on said sign data bits applied thereto from said second memory, and a latch receptive of an output data from said digital adder for applying the latched data to said second set of input terminals of said adder, an output data from said latch being the output data of said adding-and-subtracting means.